Clock distribution chip for generating both zero-delay and...

Details Clock distribution chip for generating both zero-delay and... Clock distribution chip for generating both zero-delay and...

2006-06-22

2010-02-02

Connolly, Mark (Department: 2115)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

C713S600000, C327S295000

Reexamination Certificate

active

07657773

ABSTRACT:
In one embodiment of the invention, a clock distribution (CD) chip has one or more input pins, input buffer circuitry, clock generation and distribution circuitry, fanout circuitry, one or more output pins, a feedback pin, and feedback buffer circuitry. Based on single-ended or differential input clock signals applied to the input pins, the CD chip can be programmably configured to generate zero, one, or more zero-delay (ZD) output clock signals and zero, one, or more non-zero-delay (NZD) output clock signals for simultaneous presentation at the output pins.

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