Clock distribution and control in an integrated circuit

Details Clock distribution and control in an integrated circuit Clock distribution and control in an integrated circuit

1993-09-20

1996-01-02

Westin, Edward P.

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

326101, 257208, H03K 1900, H01L 2500

Patent

active

054812097

ABSTRACT:
An apparatus and method for improved clock distribution and control in an integrated circuit which minimizes clock skew between various parts of the integrated circuit chip. Clock loads are evenly distributed between tributaries. Capacitive loading is utilized to balance any differences between tributaries and for minimizing clock skew throughout the integrated circuit.

REFERENCES:
patent: 4769558 (1988-09-01), Bach
patent: 5013942 (1991-05-01), Nishimura et al.
patent: 5077676 (1991-12-01), Johnson et al.
patent: 5122693 (1992-06-01), Honda et al.
patent: 5164817 (1992-11-01), Eisenstadt
patent: 5172230 (1992-12-01), Watanabe et al.
patent: 5270592 (1993-12-01), Takahashi et al.

Affiliated with

Also associated with

Rating

Clock distribution and control in an integrated circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Clock distribution and control in an integrated circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Clock distribution and control in an integrated circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-238049