Clock distributing circuit

Electronic digital logic circuitry – Multifunctional or programmable – Array

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395555, 326 93, G06F 104

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active

057322490

ABSTRACT:
To improve the clock delay time and skew. A first resistance body (R1) and a second resistance body (R2) are provided at a terminal end node (N5) of a clock trunk line (1) composed of a doped polysilicon film or the like. Their elements (R1), (R2) are composed of the same film as the clock trunk line (1). Their resistance ratio is set so that the clamp level may be an inverted threshold of first and second local drivers (D2, D3), and the resistance values of both resistance bodies (R1, R2), and the value of interconnection resistance (R) of the clock trunk line (1) are set so that an amplitude of a clock signal at each of the nodes (N3, N4, N5) may be a potential corresponding to 1/2 of its peak-to-peak voltage at the same time. The amplitude of the clock signal from a start end node (N3) to a terminal end node (N5) decreases, and the delay time from an output of a clock driver (D1) to outputs of the local drivers (D2, D3) shaped in waveform is much shorter, and hence the clock skew of the outputs hardly occurs.

REFERENCES:
patent: 5481209 (1996-01-01), Lim et al.
patent: 5668484 (1997-09-01), Nomura
Proc. IEEE Conference on Computer Aided Design, pp. 336-339, 1991, Ren-Song Tsay, "Exact Zero Skew".
Proc. IEEE ICCD, pp. 118-122, Oct. 1986, H.B. Bakoglu, et al., "A Symmetric Clock-Distribution Tree and Optimized High-Speed Interconnections for Reduced Clock Skew in ULSI and WSI Circuits".

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