Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-02-20
2007-02-20
Do, Thuan (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
10766954
ABSTRACT:
In a clock delay adjusting method of a semiconductor integrated circuit device, a plurality of source points for adjusting a clock delay is provided to synchronize a value of the clock delay from each of the source points of each of hierarchical blocks in a semiconductor chip to a clock input circuit operating synchronously with a clock, according to circuit design conditions of the hierarchical blocks. Area terminals are provided in the source points, respectively. A clock input terminal of the semiconductor chip and each area terminal are connected through a clock line so as to be clock distributed over a hierarchical top. A clock delay between the hierarchical blocks is adjusted.
REFERENCES:
patent: 5307381 (1994-04-01), Ahuja
patent: 5410491 (1995-04-01), Minami
patent: 5557779 (1996-09-01), Minami
patent: 5686845 (1997-11-01), Erdal et al.
patent: 5889682 (1999-03-01), Omura et al.
patent: 5978930 (1999-11-01), Furuta et al.
patent: 6020774 (2000-02-01), Chiu et al.
patent: 6053950 (2000-04-01), Shinagawa
patent: 6173435 (2001-01-01), Dupenloup
patent: 6651232 (2003-11-01), Pileggi et al.
patent: 6737903 (2004-05-01), Suzuki
patent: 5-198674 (1993-08-01), None
patent: 5-243380 (1993-09-01), None
patent: 6-140605 (1994-05-01), None
patent: 2002-76119 (2002-03-01), None
patent: 2002-245109 (2002-08-01), None
Itoh Minoru
Tajika Kenichi
Tomoshige Hiroki
Do Thuan
Levin Naum
McDermott Will & Emery LLP
LandOfFree
Clock delay adjusting method of semiconductor integrated... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Clock delay adjusting method of semiconductor integrated..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Clock delay adjusting method of semiconductor integrated... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3865105