Clock data recovery circuitry and phase locked loop...

Details Clock data recovery circuitry and phase locked loop... Clock data recovery circuitry and phase locked loop...

2006-12-12

2006-12-12

Browne, Lynne H. (Department: 2116)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

C713S501000, C713S503000

Reexamination Certificate

active

07149914

ABSTRACT:
Clock data recovery (CDR) circuitry or phase locked loop (PLL) circuitry can be provided with a dynamically adjustable bandwidth. One CDR circuit or PLL circuit can be provided to support multiple systems or protocols, multiple parameter requirements for a given system or protocol, and changes in the input frequency or data rate within a given system or protocol. The parameters can include jitter (e.g., jitter tolerance, jitter transfer, jitter generation), source of dominant noise, and lock time. Control signals can be used to dynamically adjust the bandwidth of the CDR circuitry or PLL circuitry while the circuitry is processing data. The control signals can be set by a PLD, by a processor, by circuitry external to the PLD, or by user input.

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