Clock-data recovery circuit, multi-port receiver including...

Details Clock-data recovery circuit, multi-port receiver including... Clock-data recovery circuit, multi-port receiver including...

2008-05-15

2011-11-01

Phu, Phuong (Department: 2611)

Pulse or digital communications

Synchronizers

Synchronizing the sampling time of digital data

C375S371000, C375S373000, C375S374000, C375S375000, C375S376000, C713S500000, C713S503000, C713S600000, C370S503000

Reexamination Certificate

active

08050372

ABSTRACT:
A clock-data recovery circuit includes a plurality of input ports and a code generation circuit. The plurality of input ports generates sampling clock signals based on digital control codes and samples input data signals based on the sampling clock signals to generate output data signals and phase detection signals, respectively. The code generation circuit generates the digital control codes based on the phase detection signals received from the input ports during a training mode.

REFERENCES:
patent: 5703905 (1997-12-01), Langberg
patent: 7127022 (2006-10-01), Dieguez
patent: 2006/0031701 (2006-02-01), Nam et al.
patent: 10-2006-0013206 (2006-02-01), None
patent: 10-2006-0106552 (2006-10-01), None

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