Clock data recovery circuit

Details Clock data recovery circuit Clock data recovery circuit

2003-05-01

2009-02-10

Fan, Chieh M (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S354000, C375S371000

Reexamination Certificate

active

07489757

ABSTRACT:
A frequency divider generates frequency-divided input data by dividing a frequency of input data. A phase comparator detects a phase difference between a phase of a clock generated by a voltage control oscillator and a phase of the frequency-divided input data, and generates a phase difference signal to be used to eliminate the detected phase difference. The voltage control oscillator generates the clock by adjusting an oscillation frequency based on the phase difference signal. A data identifier identifies the input data using the clock generated by the voltage control oscillator.

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Ansgar Pottbacker et al., “A Si Bipolar Phase and Frequency Detector IC for Clock Extraction up to 8GB/s”, IEEE Journal of Solid State Circuits , Dec. 1992, vol. SC-27, pp. 1747-1751.

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