Clock control system and method using circuitry operating at low

Details Clock control system and method using circuitry operating at low Clock control system and method using circuitry operating at low

1995-03-29

1998-05-26

Dung, Dinh C.

Electronic digital logic circuitry

Multifunctional or programmable

Array

395553, 39518209, 326 93, G06F 106, G06F 112

Patent

active

057581320

ABSTRACT:
First and second parallel processors operate in one of plural modes including synchronous and stand-alone modes. Each processor includes a clock for selectively providing a first high frequency clock signal to both processors. Each processor also includes electronic circuitry operating at a second frequency lower than the first frequency which generates a clock selection signal that selects one of the clocks from the first and second processors to clock both processors. The electronic circuitry, in response to mode change signals, generates clock switching control signals at the lower frequency. The lower frequency clock control signals are reclocked so that they are synchronous with the first frequency clock signals before being used to select one of the clocks.

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