Clock control of state storage circuitry

Details Clock control of state storage circuitry Clock control of state storage circuitry

2011-02-22

2011-02-22

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C327S218000, C714S732000

Reexamination Certificate

active

07893722

ABSTRACT:
State storage circuitry is described comprising a master-slave latch having tristate inverter circuitry2at its functional input and tristate scan signal insertion circuitry12for inserting scan data. The tristate scan signal insertion circuitry12is controlled by a first clock signal nclk and a second clock signal bclk. The tristate inverter circuitry2is controlled by a third clock signal nfclk and a fourth clock signal flck. The clock generating circuitry holds the third and fourth clock signals at fixed values which tristate the tristate inverter circuitry2when in scan mode. This moves scan control logic out of the function path comprising the tristate inverter circuitry into the clock control circuitry.

REFERENCES:
patent: 5999030 (1999-12-01), Inoue
patent: 7292672 (2007-11-01), Isono
patent: 2005/0268191 (2005-12-01), Shin
patent: 2007/0103217 (2007-05-01), Frederick et al.
patent: 2008/0115025 (2008-05-01), Frederick
patent: 2009/0015321 (2009-01-01), Hamdan et al.
patent: 2010/0083062 (2010-04-01), Huang et al.

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