Clock control method, frequency dividing circuit and PLL...

Details Clock control method, frequency dividing circuit and PLL... Clock control method, frequency dividing circuit and PLL...

2006-05-30

2006-05-30

Phu, Phuong (Department: 2631)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S374000, C375S375000, C331S025000

Reexamination Certificate

active

07054404

ABSTRACT:
A PLL circuit includes a phase comparator; a charge pump; a loop filter; a voltage-controlled oscillator; a frequency dividing circuit; an A counter for dividing the P-frequency-divided output; circuits for generating two signals, which have a phase difference equivalent to one period of the P-frequency-divided output of the frequency dividing circuit; and an interpolator for producing an output signal obtained by interpolating the phase difference between the two signals in accordance with an interior division ratio. The interpolator interpolates in steps of a value obtained by dividing the phase difference by P and incrementing or decrementing a value B, which decides an interior division ratio B:P−B, by B whenever frequency-division by A is performed, and a control circuit. The phase of the output of the interpolator is fed to the phase comparator and compared with the phase of a reference clock, and divides by a frequency-dividing factor.

REFERENCES:
patent: 4484153 (1984-11-01), Borras et al.
patent: 5349310 (1994-09-01), Rieder et al.
patent: 5889437 (1999-03-01), Lee
patent: 6066990 (2000-05-01), Genest
patent: 6-69788 (1994-03-01), None
patent: 6-120815 (1994-04-01), None

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