Clock control circuit that generates and selects one of a...

Details Clock control circuit that generates and selects one of a... Clock control circuit that generates and selects one of a...

2006-03-07

2009-06-09

Patel, Nitin C (Department: 2116)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

C713S501000, C713S502000

Reexamination Certificate

active

07546481

ABSTRACT:
A clock control circuit including a divider unit for dividing a master clock signal at a falling timing of the same to generate a divided clock signal, a multiplier unit for multiplying the master signal by n at a rising timing of the same, and thinning out an n-th clock pulse to generate a multiplied clock signal, and a selector unit for selecting a bus clock signal from multiplied clock signals at a variety of timings, derived from the multiplied clock signal, and the divided clock signal in accordance with a selection signal, and supplying the selected signal to a processor.

REFERENCES:
patent: 6779125 (2004-08-01), Haban
patent: 2002-215570 (2002-08-01), None

Affiliated with

Also associated with

Rating

Clock control circuit that generates and selects one of a... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Clock control circuit that generates and selects one of a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Clock control circuit that generates and selects one of a... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4102229