Clock control circuit and method

Details Clock control circuit and method Clock control circuit and method

2006-09-05

2006-09-05

Lin, Sun James (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07103855

ABSTRACT:
A clock reproduction circuit for reproducing a data clock from a data signal is disclosed. The clock reproduction circuit includes a voltage controlled oscillator, a phase detector, a frequency error detection circuit and a charge pump whose output is controlled by the outputs of the phase detector and the frequency error detection circuit. A VCO clock output from the voltage controlled oscillator is synchronized with the data clock by the beedback loop consisting of these elements. The frequency error detection circuit detects a frequency error between the VCO clock and the data clock by detecting changes in the phases of the VCO clock at the transition edges of the data signal. Analog and digital frequency error detection circuits are disclosed. Further, improved circuit elements in the clock reproduction circuit are disclosed.

REFERENCES:
patent: 5210700 (1993-05-01), Tom
patent: 5801780 (1998-09-01), Schaumont et al.
patent: 6052004 (2000-04-01), Saeki
patent: 6066969 (2000-05-01), Kawasaki et al.
patent: 6094076 (2000-07-01), Saeki
patent: 6173432 (2001-01-01), Harrison
patent: 6181174 (2001-01-01), Fujieda et al.
patent: 6194930 (2001-02-01), Matsuzaki et al.
patent: 6239633 (2001-05-01), Miyano
patent: 11-4145 (1999-01-01), None
patent: 11-4146 (1999-01-01), None
patent: 11-205129 (1999-07-01), None
patent: 11-355131 (1999-12-01), None
patent: 2000-124795 (2000-04-01), None
patent: 2000-163968 (2000-06-01), None
patent: 271023 (1996-02-01), None
Horowitz, M. et al, “PLL Design for a 500 MB/s Interface”, IEEE, ISSCC 93, Session 10, pp. 160-161.
Sidiropoulos, S. et al, “A Semi-Digital DLL wit h Unlimited Phase Shift Capability and 0.08-400MHz Operating Range”, 1997 IEEE, ISSCC 97, Session 20, pp. 332-333.

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