Clock circuitry architecture to improve electro-magnetic...

Details Clock circuitry architecture to improve electro-magnetic... Clock circuitry architecture to improve electro-magnetic...

2007-01-30

2010-02-23

Lee, Thomas (Department: 2115)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

Correction for skew, phase, or rate

C713S500000, C713S501000, C713S502000

Reexamination Certificate

active

07669072

ABSTRACT:
A system comprises a central processing unit and a set of peripheral units accessible by the CPU and being able to be driven by the same clock source. At least one programmable delay line is located in the clock branch of one of the peripheral units and has a delay selection input that is accessible by software running on the system.

REFERENCES:
patent: 5675832 (1997-10-01), Ikami et al.
patent: 6275068 (2001-08-01), Kermani et al.
patent: 6289468 (2001-09-01), Godfrey
patent: 7477068 (2009-01-01), Truong et al.
patent: 2004/0056699 (2004-03-01), Truong et al.
patent: 2005/0218953 (2005-10-01), Slawecki
patent: WO-2008094961 (2008-08-01), None
patent: WO-2008094961 (2008-08-01), None
“International Application Serial No. PCT/US2008/052391, Search Report and Written Opinion mailed Jul. 14, 2008” 10 pages.

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