Clock circuit for reading a multilevel non volatile memory cells

Details Clock circuit for reading a multilevel non volatile memory cells Clock circuit for reading a multilevel non volatile memory cells

1997-06-27

1999-11-16

Fears, Terrell W.

Static information storage and retrieval

Systems using particular element

Capacitors

365233, G11C 1300

Patent

active

059869216

ABSTRACT:
A timing circuit for reading from a device comprising multi-level non-volatile memory cells, which circuit comprises a single programmable delay block connected to an input terminal for memory address line transition signals. The delay block drives a counter which feedback controls the discharge through a combinational logic circuit connected to the output terminal of the programmable delay block. A logic output circuit, connected to the output terminal of the delay block and to the counter, generates the timing signals.

REFERENCES:
patent: 3712994 (1973-01-01), Graziani
patent: 4425553 (1984-01-01), LaPierre
patent: 4504749 (1985-03-01), Yoshida
patent: 4604513 (1986-08-01), Lim
patent: 4939382 (1990-07-01), Gruodis
patent: 5144156 (1992-09-01), Kawasaki

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