Clock circuit and method of designing the same

Details Clock circuit and method of designing the same Clock circuit and method of designing the same

2000-09-18

2002-10-29

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C326S046000, C326S047000, C326S093000, C327S144000

Reexamination Certificate

active

06473890

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a clock circuit utilizing a clock delay and a method of designing the same.
For easy adjustment of the input/output timing, an increasing number of semiconductor integrated circuits (LSIs: hereinafter referred to as circuits) have adopted a synchronous design method in which signal transfer in a circuit is performed in synchronization with a clock signal.
Since the synchronous design method normally assumes simultaneous supply of a clock signal to each of synchronous devices, designing a circuit such that a maximum delay in signal processing (signal critical path delay) falls within a clock period ensures the operation of the entire circuit.
The arrival times of the clock signal at the individual synchronous devices, i.e., the difference between clock delay values are termed skew (clock skew). In the synchronous design method, it is required to design a clock circuit (portion of the circuit used to transmit and receive the clock signal) with zero skew.
As a representative of the synchronous design method, there has been proposed a method of designing a clock circuit wherein the number of devices and a wiring length are equal in each of clock signal supply paths extending from a clock source to the individual synchronous devices, such as one disclosed in U.S. Pat. No. 5,849,610 (Qing Zhu, “Method for Constructing a Planar Equal Path Length Clock Tree”, 1998).
It is to be noted that a signal delay is determined by a device delay DD and a wiring delay WD in a signal propagation path. With process variations during LSI fabrication or ambient variations such as voltage or temperature variations during LSI operation, the device delay DD undergoes a variation of &Dgr;DD per unit device and the wiring delay WD undergoes a variation of &Dgr;WD per unit wiring length.
Since the number of devices and the wiring length are equal in each of the clock signal supply paths in the aforementioned method of designing an equal path length clock circuit, the signal delay in each of the clock signal supply paths varies in the same manner so that the clock signal is supplied, while the skew is held minimum against the process variations, the temperature variations, or the like.
FIG. 25
shows variations in device delay, wiring delay, and signal delay resulting from temperature variations.
In
FIG. 25
, the graph plotted as the fine solid line represents variations in device delay (transistor delay) Dtr, the graph plotted as the fine broken line represents variations in wiring delay Dwr, the graph plotted as the thick solid line represents variations in first signal delay Dp
1
in a first signal supply path in which the wiring delay is longer than the device delay, and the graph plotted as the thick broken line represents variations in second signal delay Dp
2
in a second signal supply path in which the device delay is longer than the wiring delay. In
FIG. 25
, the horizontal axis represents temperature and the vertical axis represents delay time. Room temperature is designated at room (the dot-dash line in the drawing). A temperature lower than the room temperature and a temperature higher than the room temperature are designated at Tcool and Thot, respectively.
As shown in
FIG. 25
, if the proportion of device delay to wiring delay is different from one signal supply path to another, the variations in signal delay resulting from the variations in temperature are also different. By providing an equal proportion of device delay to wiring delay in each of the clock signal supply paths, i.e., by providing an equal number of devices and an equal wiring length in each of the clock signal supply paths, it is possible to provide an equal clock delay in each of the synchronous devices against the temperature variations.
However, with an increase in the number of devices integrated in an LSI and a relative increase in wiring resistance resulting from miniaturization, it has become extremely difficult to generate a clock circuit in which an equal number of devices and an equal wiring length is provided in each of clock signal supply paths. In other words, it has become difficult to design a clock circuit with zero clock skew. If clock skew is produced in the synchronous design method, the individual synchronous devices receive the signal at different times. As a result, part of signal transfer is not completed within a reception time so that the phenomenon of so-called mislatch (reception of a signal different from a target signal) occurs. Consequently, the circuit cannot perform correct signal transfer any more.
If a wire width larger than 0.5 &mgr;m is used in semiconductor fabrication, the conventional synchronous design method, i.e., the zero skew clock design method can ignore the influence of a wiring resistance R on the clock delay, which allows the clock delay to be regarded as a time required by the driving device to supply charge equal to the wiring capacitance (including an input terminal capacitance at a signal reception point).
If a wire width smaller than 0.5 &mgr;m is used in semiconductor fabrication, on the other hand, the influence of the wiring resistance R on the clock delay cannot be ignored any more. According to the approximation by Elmore (W. C. Elmore, “The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers”, Journal of Applied Physics, Vol.19, 1948, pp.55-63), the wiring delay from a point P
1
to a point P
2
is proportional to the wiring resistance R
1
from the point P
1
to the point P
2
and a total wiring capacitance (total wiring charge capacitance) C of the point P
2
and its successors. Even if the circuit is designed such that each of the clock signal supply paths has an equal total wiring capacitance C
0
, clock delays (combination of R and C) in the individual synchronous devices are different depending on the configuration of branch lines, a wire width, or the like so that an increase in skew is unavoidable in the conventional zero skew clock design method.
As an example of a method of solving the foregoing problem caused by the introduction of miniaturization technology, while retaining the advantages of the conventional synchronous design method, Japanese Unexamined Patent Publication No. HEI 9-63291 (Yoda, Iida, Sasano, et al., “clock Distributing Method”, 1997) discloses a method wherein logic design and clock circuit design are performed sequentially based on a zero skew clock circuit and then a skew value is calculated. Thereafter, a clock supply source is adjusted in accordance with a shortest delay in the synchronous devices to ensure the operation of the entire circuit. On the other hand, U.S. Pat. No. 5,896,299 (Arnold Ginetti et al., “Method and System for Fixing Hold Time Violations in Hierarchical Designs”, 1999) proposes a method wherein logic design and clock circuit design are performed sequentially based on a zero skew clock circuit and then delay analysis is performed based on the result of the layout as the result of the design processes. Thereafter, a logic circuit is designed again by assuming that the clock skew from the clock source to each of the synchronous devices is Ts to ensure the operation of the entire circuit.
However, since each of the methods proposed by Japanese Unexamined Patent Publication No. HEI 9-63291 and U.S. Pat. No. 5,896,299 is based on the conventional zero skew clock circuit and aims at ensuring circuit operation by compensating the clock circuit or logic circuit, the foregoing problem caused by the introduction of miniaturization technology cannot be solved completely.
Besides the methods proposed by Japanese Unexamined Patent Publication No. HEI 9-63291 and U.S. Pat. No. 5,896,299, a semi-synchronous design method (Yoda, Sasaki, Takahashi, et al., “Clock Scheduling with Consideration of Modification Cost in Semi-Synchronous Circuit”, Technical Report of Institute of Electronics, Information and Communication Engineers, CAS99-36, pp.45-52, 1999) has been proposed as a method of improving circuit performance, which is not

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