Clock change circuit preventing spike generation by delaying sel

Details Clock change circuit preventing spike generation by delaying sel Clock change circuit preventing spike generation by delaying sel

1995-02-22

1996-11-26

Tse, Young T.

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

375359, 327 99, 327153, 327161, 326 93, 3701053, H04L 700

Patent

active

055793509

ABSTRACT:
A clock change circuit contains: a clock gate unit for receiving first and second clock signals, and detecting a timing at which both the first and second clock signals are at an inactive level to output an active timing signal indicating the timing; a delay unit for inputting a select control signal and the timing signal, and outputting a delayed select control signal the state of which is changed to the same state of the select control signal after the active timing signal is received from the clock gate unit; and a select unit for inputting the first and second clock signals, and selects one of the first and second clock signals according to the delayed select signal to output the selected clock signal.

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