Clock buffer circuit

Details Clock buffer circuit Clock buffer circuit

2011-07-26

2011-07-26

Crawford, Jason M (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S098000

Reexamination Certificate

active

07986166

ABSTRACT:
A clock buffer for a clock network that reduces leakage current and lowers power consumption. The clock buffer includes a first CMOS transistor, a second CMOS transistor, and a leakage current prevention circuit connected to the first and second CMOS transistors. The leakage current prevention circuit includes a first PMOS transistor, which is connected between the source of a PMOS transistor of the first CMOS transistor and a power supply line, and a second PMOS transistor, which is connected between the source of a PMOS transistor of the second CMOS transistor and the power supply line. The first and second PMOS transistors are deactivated in response to an enable signal generated when a circuit block does not require the clock signal. The first and the second PMOS transistors have predefined widths and lengths such that the addition of these transistors in series with the CMOS transistors does not increase the propagation delay of the clock buffer circuit. Deactivating the first and second PMOS transistors disconnects the CMOS transistors from the power supply line, which prevents current leakage.

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