Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
1999-10-25
2001-02-27
Mai, Son (Department: 2818)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S233100
Reexamination Certificate
active
06195303
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to integrated circuits, and more articularly to clock-based, transparent refresh dynamic random access memories (DRAMs).
Dynamic random access memories often include a large number of memory cells, each of which is typically implemented with a capacitor coupled to a bit line via a switch. The capacitor holds a charge that is indicative of the data value being stored. By selectively coupling the capacitor to the bit line, the charge stored on the capacitor can be detected and the data value ascertained.
Due to various physical phenomenons, the charge stored on the memory cell capacitor slowly leaks over time. To avoid loss of data, the capacitor is periodically refreshed (or recharged) to a full value. Failure to refresh the memory cell within a particular time period (sometimes referred to as a critical time period) can lead to sufficient loss of charge from the capacitor such that the correct data value cannot be accurately ascertained.
Several schemes have been developed to systematically refresh memory cells in a DRAM. A command refresh scheme performs refresh of specific sections of the DRAM upon receiving a refresh command. A self-refresh scheme performs refresh of the DRAM based on self-initiated action. Both of these schemes typically require the DRAM to stop its activities while doing the refresh. Since the DRAM often includes a large number of rows and the refresh is sometimes staggered for various considerations (i.e., power consumption), the overhead to perform refresh can consume a noticeable percentage of the available operating time, which translates to a reduction in the data bandwidth.
Accordingly, efficient DRAM refresh schemes are highly desirable.
SUMMARY OF THE INVENTION
The invention provides clock-based “transparent” refresh mechanisms for (e.g., synchronous) DRAM. In the transparent refresh mode, the DRAM internally and periodically generates a command to refresh while it is operating in normal manner and servicing memory accesses. The refresh command can be generated based on a clock signal or other control signals provided to the DRAM. Transparent refreshes are performed on the memory cells within a critical time period before the risk (i.e., probability) of data loss due to cell capacitor leakage exceeds a particular threshold.
An embodiment of the invention provides a refresh control circuit for a DRAM that includes a timing circuit, a control logic, an address generator, and a multiplexer. The timing circuit provides a refresh enable signal that can be based on, for example, one or more received operational signals (e.g., a clock signal CLK, a clock enable signal CKE, or others) or an idle signal that indicates that the DRAM is idle. The control logic receives the refresh enable signal and a command control signal and provides a refresh control signal. The address generator receives the refresh control signal and provides a refresh address. The multiplexer receives the refresh address and an external address and provides one of the received addresses as an output address. The refresh control circuit initiates refresh of selected memory cells within the DRAM in time periods between memory accesses of the DRAM.
The refresh control circuit can further include a command decoder and a comparator. The command decoder receives an external command signal and generates the command control signal that indicates a memory access of the DRAM. The comparator receives the external address and the refresh address and generates an indicator signal that indicates whether the received addresses are the same.
Another embodiment of the invention provides a refresh control circuit for a DRAM that includes a timing circuit coupled to at least one row control circuit. The timing circuit provides a refresh enable signal. Each row control circuit receives the refresh enable signal and a command control signal and provides a respective output address. Each row control circuit includes a control logic, an address generator, and a multiplexer that operate in a manner similar to that described above. Each row control circuit can further include a comparator that also operates in a manner similar to that described above. The refresh control circuit can initiate refresh of selected memory cells within the DRAM in time periods between memory accesses of the DRAM.
In a specific implementation of this embodiment, the refresh control circuit includes two or more row control circuits that are capable of providing, when enabled, refresh addresses to respective sections of the DRAM associated with the row control circuits. Each row control circuit can be associated with, for example, a bank of memory or a block of memory. The comparator in each row control circuit provides a respective indicator signal that indicates whether the refresh address generated by that row control circuit is the same as the external address.
Yet another embodiment of the invention provides a memory device that includes a row decoder, a column decoder, a number of memory arrays, and a refresh control circuit. The row and column decoders respectively receive first and second portions of address information and generate first and second sets of control signals, respectively. The memory arrays couple to the row and column decoders and provide one or more data values in response to the first and second sets of control signals. The refresh control circuit couples to the row decoder and provides the first portion of address information for memory accesses and refresh operations. The refresh control circuit initiates refresh of selected memory cells within the memory device in time periods between memory accesses. The refresh control circuit can be implemented using, for example, any of the embodiments described above.
Another embodiment of the invention provides a method for performing refresh of a memory cell within a memory circuit. In accordance with the method, a refresh enable signal is generated within the memory circuit and in time periods between memory accesses of the memory circuit. A refresh control signal is generated in response to the refresh enable signal and a command control signal. A refresh address is generated based, in part, on the refresh control signal. The refresh address indicates the locations of memory cells to be refreshed. Either the refresh address or an external address is then selected and provided as an output address.
For the above embodiments, the refresh enable signal can be activated: (1) periodically based on a received clock signal, (2) by an idle signal that indicates that the memory device is idle, (3) by an external command to refresh, by other mechanisms, or by a combination thereof.
The foregoing, together with other aspects of this invention, will become more apparent when referring to the following specification, claims, and accompanying drawings.
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patent: 5881011 (1999-03-01), Son
Dinh & Associates
Mai Son
Winbond Electronics Corporation
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