Clock aware placement

Details Clock aware placement Clock aware placement

2006-10-31

2009-11-24

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

07624366

ABSTRACT:
The layout of latches in a common clock domain is efficiently optimized to shrink the physical size of the domain while maintaining timing requirements. The latches are placed in a first layout preferably using quadratic placement, and a star object is built representing an interim clock structure. The latches are weighted based on wire distance from a source of the star object, and then re-placed using the weighting. The weighted placement and repartitioning may be iteratively repeated until a target number of bins is reached. The boundary of the latches in the final global placement is used to define a movebound for further detailed placement.

REFERENCES:
patent: 5917729 (1999-06-01), Naganuma et al.
patent: 6182269 (2001-01-01), Laubhan
patent: 6536024 (2003-03-01), Hathaway
patent: 7024636 (2006-04-01), Weed
Viswanathan et al., “FastPlace: Efficient Analytical Placement using CellShifting, Iterative Local Refinement and a Hybrid Net Model”, ISPD'04, Apr. 18-21, 2004, Phoenix, Arizona, USA. Copyright 2004 ACM 1-58113-817-02/04/0004.
Y. Lu et al., “Navigating Registers in Placement for Clock Network Minimization,” ACM proceedings (DAC) pp. 176-181 (2005).

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