Clock architecture for a frequency-based tester

Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis

Reexamination Certificate

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Details

C375S371000, C375S376000, C375S356000, C375S327000, C375S140000, C375S152000

Reexamination Certificate

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06976183

ABSTRACT:
A clock system is disclosed for distributing and generating a digital clock signal for a plurality of electronic assemblies. The clock system includes a remote fixed-frequency clock for generating a first clock signal of a first frequency and a plurality of local clock modules. The local clock modules are respectively disposed on the plurality of electronic assemblies and each include synthesizer circuitry for creating a variable clock signal of a different frequency than the first frequency. Fanout circuitry is coupled between the remote fixed frequency clock and the plurality of local clock modules to distribute the first clock signal.

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L. Ashby, Asic Clock Distribution Using a Phase Locked Loop (PLL), Sep. 1991, pp. P1-6.1-6.3, IEEE, New York, NY.

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