Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output process timing
Reexamination Certificate
2005-11-02
2008-10-14
Peyton, Tammara R (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output process timing
C710S008000, C710S030000, C710S051000, C710S052000, C365S001000
Reexamination Certificate
active
07437491
ABSTRACT:
Improved clock and data recovery involves transmitting one or more null frames prior to transmitting a sync frame. A receiving component detects for the sync frame to lock to a data signal sent on a signal path by a transmitting component. The one or more null frames transmitted prior to the sync frame results in a settling of the signal path prior to reception of the sync frame, thereby lessening or removing the effects of previously sent data on the sync frame.
REFERENCES:
patent: 6195393 (2001-02-01), Nemiroff et al.
Bau Jason H.
Huang Dawei
Risk Gabriel C.
Osha & Liang LLP
Peyton Tammara R
Sun Microsystems Inc.
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