Clock and data recovery unit

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction

Reexamination Certificate

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Details

C375S354000, C375S371000, C375S375000, C375S376000, C327S001000, C709S248000

Reexamination Certificate

active

07457391

ABSTRACT:
A clock and data recovery unit for recovering a received serial data bit stream having: phase adjustment means for adjustment of a sampling time in the center of a unit interval of the received data bit stream, wherein the phase adjustment means comprises means for generating equidistant reference phase signals, a phase interpolation unit, an oversampling unit, a serial-to-parallel-conversion unit, a binary phase detection unit, and a loop filter; and data recognition means for recovery of the received data stream which includes a number of parallel data recognition FIR-Filters, wherein each data recognition FIR-Filter comprises a weighting unit, a summing unit, and a comparator unit.

REFERENCES:
patent: 6646822 (2003-11-01), Tuttle et al.
patent: 7149269 (2006-12-01), Cranford et al.
patent: 7197102 (2007-03-01), Rhee et al.
patent: 7292662 (2007-11-01), Gregorius
patent: 2002/0080898 (2002-06-01), Agazzi et al.
patent: 2006/0181797 (2006-08-01), Sugawara et al.
patent: 19922804 (1999-11-01), None
patent: WO97/28624 (1997-08-01), None

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