Clock and data recovery circuits utilizing digital delay...

Details Clock and data recovery circuits utilizing digital delay... Clock and data recovery circuits utilizing digital delay...

2006-10-24

2006-10-24

Ha, Dac V. (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S376000, C327S155000, C327S158000, C327S159000, C327S161000

Reexamination Certificate

active

07127022

ABSTRACT:
Clock and data recovery (CDR) circuits that are fully digital. A data stream encoded with clocking information is passed through a tapped digital delay line. A phase and frequency detector coupled to the registered outputs of the tapped digital delay line determines the phase and frequency relationship between the recovered clock (DCO clock) and the transmit clock. A filter and control circuit then uses this information to generate a “servo” control signal, which is passed through a dither circuit and fed back to a digitally controlled oscillator (DCO). The circuit adjusts the DCO clock signal to match the transmit clock based on the value of this control signal.

REFERENCES:
patent: 6348823 (2002-02-01), Pan
patent: 6686784 (2004-02-01), Chang

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