Clock and data recovery circuit having wide phase margin

Details Clock and data recovery circuit having wide phase margin Clock and data recovery circuit having wide phase margin

2011-06-14

2011-06-14

Payne, David C. (Department: 2611)

Pulse or digital communications

Synchronizers

Synchronizing the sampling time of digital data

C375S371000

Reexamination Certificate

active

07961830

ABSTRACT:
A clock and data recovery (CDR) circuit includes a sampler, a CDR loop and a phase interpolator. The sampler samples serial data in response to a recovery clock signal to generate a serial sampling pulse. The CDR loop transforms the serial sampling pulse into parallel data, generates a plurality of phase signals with a first speed based on the parallel data, and generates a phase control signal with a second speed higher than the first speed based on the plurality of phase signals. The phase interpolator generates the recovery clock signal by controlling a phase of a reference clock signal in response to the phase control signal. Therefore, the CDR circuit may recover data and a clock with a relatively high speed.

REFERENCES:
patent: 3665380 (1972-05-01), Stover
patent: 5420868 (1995-05-01), Chraplyvy et al.
patent: 5535252 (1996-07-01), Kobayashi
patent: 6002279 (1999-12-01), Evans et al.
patent: 6122336 (2000-09-01), Anderson
patent: 2002/0044618 (2002-04-01), Buchwald et al.
patent: 2004/0252804 (2004-12-01), Aoyama
patent: 2005/0270214 (2005-12-01), Seknicka
patent: 11-289250 (1999-10-01), None
patent: 2004-260867 (2004-09-01), None
patent: 1020040109971 (2004-12-01), None
Stefanos Sidiropoulos and Mark A. Horowitz, IEEE Journal of Solid-State Circuits, vol. 32, No. 11, Nov. 1997, “A Semidigital Dual Delay-Locked Loop” pp. 1683-1692.

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