Clock and data recovery circuit having gain control

Details Clock and data recovery circuit having gain control Clock and data recovery circuit having gain control

2006-02-03

2009-11-17

Ha, Dac V (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S345000, C375S375000, C327S146000, C327S155000

Reexamination Certificate

active

07620136

ABSTRACT:
A clock and data recovery circuit includes a phase detector configured to compare a phase of a data signal to a phase of a sampling clock to provide a phase error signal, a gain stage configured to apply a gain to the phase error signal to provide an amplified phase error signal, and a filter configured to filter the amplified phase error signal to provide a phase correction signal. The circuit includes a gain controller configured to adjust the gain of the gain stage in response to the phase correction signal, and a clock generator configured to provide the sampling clock based on the phase correction signal.

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Jri Lee et al., “Analysis and Modeling of Bang-Bang Clock and Data Recovery Circuits”,IEEE Journal of Solid-State Circuits, vol. 39, No. 9, Sep. 2004. pp. 1571-1580.

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