Clock and data recovery circuit and method

Details Clock and data recovery circuit and method Clock and data recovery circuit and method

2007-08-07

2007-08-07

Ha, Dac (Department: 2611)

Pulse or digital communications

Synchronizers

C375S326000, C375S327000, C375S355000, C375S376000

Reexamination Certificate

active

10634279

ABSTRACT:
In a clock and data recovery circuit and method, the clock and data recovery circuit comprises a clock signal generator for generating N clock signals, each clock signal having phase difference of 360/N×K from each other, wherein the N denotes an integer and the K denotes an integer from 0 to N−1, a phase selector for generating an I+2thclock signal out of the N clock signals as a recovered clock signal if an Ithclock signal is on a first state and an I+1thclock signal is on a second state when logic level transition of a received data is detected, wherein the I denotes an integer from 1 to N, and a recovered data generator for generating a recovered data synchronized with the recovered clock signal by using the received data in response to the recovered clock signal output from the phase selector.

REFERENCES:
patent: 5928293 (1999-07-01), Jobling et al.
patent: 6584163 (2003-06-01), Myers et al.
patent: 6954506 (2005-10-01), Cho

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