Clock and data recovery circuit

Details Clock and data recovery circuit Clock and data recovery circuit

2005-10-18

2005-10-18

Bocure, Tesfaldet (Department: 2631)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

Reexamination Certificate

active

06956921

ABSTRACT:
The invention concerns a clock and data recovery circuit as well as a method for clock and data recovery using three or more clock phases of a reference clock for locking a data signal and the clock signal yielding a very stable phase alignment of the data and clock signals. In accordance with the invention, two of the clock phases are selected to be 180 degrees out of phase with the third clock phase, plus or minus a parameter M. The data signal is sampled at each of the three or more clock phases and a phase selection signal is generated based on a truth table. The state of the data signal in a previous cycle may further be included in the truth table.

REFERENCES:
patent: 3746800 (1973-07-01), Stuart
patent: 4821297 (1989-04-01), Bergmann et al.
patent: 5247544 (1993-09-01), LaRosa et al.
patent: 5870441 (1999-02-01), Cotton et al.
patent: 6424684 (2002-07-01), Baker
European Search Report, dated Mar. 08, 2000.

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