Clock and clock adjustment circuit for minimum jitter

Details Clock and clock adjustment circuit for minimum jitter Clock and clock adjustment circuit for minimum jitter

2011-08-23

2011-08-23

Ha, Dac (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

Reexamination Certificate

active

08005181

ABSTRACT:
A method for adjusting a clock for a jitter sensitive circuit begins by determining a low noise phase region of a primary clock. The method then continues by adjusting phase of an auxiliary clock such that a transition of the auxiliary clock falls within the low noise phase region of the primary clock to produce an adjusted auxiliary clock.

REFERENCES:
patent: 6285726 (2001-09-01), Gaudet
patent: 6525578 (2003-02-01), Ooishi
patent: 6545507 (2003-04-01), Goller
patent: 6812731 (2004-11-01), Trimberger
patent: 7127017 (2006-10-01), Evans et al.
patent: 2002/0140472 (2002-10-01), Sonobe
patent: 2002/0154723 (2002-10-01), Nakamura
patent: 2005/0278131 (2005-12-01), Rifani et al.

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