Clipped sine wave channel erase method to reduce oxide trapping

Details Clipped sine wave channel erase method to reduce oxide trapping Clipped sine wave channel erase method to reduce oxide trapping

1999-10-20

2000-09-19

Nelms, David

Static information storage and retrieval

Floating gate

Particular biasing

36518519, 36518526, 36518527, G11C 1604

Patent

active

061222011

ABSTRACT:
A method to channel erase data from a flash EEPROM while electrical charges trapped in the tunneling oxide of a flash EEPROM are eliminated to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. The method to channel erase a flash EEPROM cell begins by removing the charge from the floating gate of the flash EEPROM cell. The channel erasing consists of applying a relatively large clipped sinusoidal negative voltage pulse to the control gate of said EEPROM cell and concurrently applying a moderately large positive voltage pulse to a first diffusion region. At the same time a ground reference potential is applied to the semiconductor substrate, while the drain, the source and a second diffusion well are allowed to float.

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patent: 5828605 (1998-10-01), Peng et al.
patent: 5838618 (1998-11-01), Lee et al.
patent: 5862078 (1999-01-01), Yeh et al.

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