Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-07-10
2007-07-10
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
10470402
ABSTRACT:
An automated method for producing integrated circuit arrangements for automotive vehicle control systems provides at least two logically isolated subsystems (5, 6) and, in addition to the logical isolation, effects a spatial (physical) isolation of the subsystems on the surface available on the circuit arrangement.
REFERENCES:
patent: 6185721 (2001-02-01), Hosokawa
patent: 6275752 (2001-08-01), Giers
Bannatyne, R., “Dependable auto systems emerge,” EE Times, Jul. 28, 2000, 4 pages, http://www.eetimes.com/story/OEG20000728S0023.
R.E. Lyons et al., “The Use of Triple-Modular Redundancy to Improve Computer Reliability,” IBM journal, Apr. 1962, pp. 200-209.
S.E. Smith, “Triple Redundant Fault Tolerance: A Hardware-Implemented Approach,” ISA Transactions, vol. 30, No. 4, 1991, pp. 87-95.
Continental Teves AG & Co, oHG
Garbowski Leigh M.
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