Clearance hole size adjustment for impedance control in...

Details Clearance hole size adjustment for impedance control in... Clearance hole size adjustment for impedance control in...

2007-09-18

2007-09-18

Pascal, Robert (Department: 2817)

Wave transmission lines and networks

Coupling networks

With impedance matching

C333S017300, C333S263000

Reexamination Certificate

active

11160785

ABSTRACT:
The present invention provides a technique for adjusting the size of clearance holes for impedance control in multilayer electronic packaging and printed circuit boards. The method comprises: providing parameters for a structure having a clearance hole and at least one via passing through the clearance hole; calculating a characteristic impedance for the at least one via; and adjusting at least a size of the clearance hole until the characteristic impedance for the at least one via is approximately equal to a desired characteristic impedance.

REFERENCES:
patent: 5797765 (1998-08-01), Barnett et al.
patent: 6023211 (2000-02-01), Somei
patent: 6486755 (2002-11-01), Aruga
patent: 6787710 (2004-09-01), Uematsu et al.
patent: 6950066 (2005-09-01), Hendler et al.
patent: 7045719 (2006-05-01), Alexander et al.
patent: 2005/0146390 (2005-07-01), Baek

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