Photography – Fluid-treating apparatus – Having testing – calibration – or indicating
Reexamination Certificate
2000-04-26
2001-02-20
Rutledge, D. (Department: 2851)
Photography
Fluid-treating apparatus
Having testing, calibration, or indicating
C396S579000
Reexamination Certificate
active
06190062
ABSTRACT:
TECHNICAL FIELD
The present invention generally relates to improving critical dimension measurements. In particular, the present invention relates to incorporating a cleaning chamber into a scanning electron microscope to reduce the number of charged defects that interfere with measuring critical dimension.
BACKGROUND ART
Microlithography processes for making miniaturized electronic components, such as in the fabrication of computer chips and integrated circuits, are of increasing importance as the trend towards miniaturization and integration continues. Lithography involves the use of resists to temporarily mask a semiconductor substrate surface to enable site specific additive, subtractive, or enhancing processing (e.g., deposition, etching, doping). Lithography specifically involves applying a coating or film of a resist to a substrate material, such as a silicon wafer used for making integrated circuits. The substrate may contain any number of layers or devices thereon.
The resist coated substrate is baked to evaporate any solvent in the resist composition and to fix the resist coating onto the substrate. The baked coated surface of the substrate is next subjected to selective radiation; that is, an image-wise exposure to radiation. This radiation exposure causes a chemical transformation in the exposed areas of the resist coated surface. Types of radiation commonly used in microlithographic processes include visible light, ultraviolet (UV) light and electron beam radiant energy. After selective exposure, the resist coated substrate is treated with a developer solution to dissolve and remove either the radiation-exposed or the unexposed areas of the resist (depending upon whether a positive resist or a negative resist is utilized) resulting in a patterned or developed resist. Many developer solutions contain water and a base, such as water and a hydroxide compound.
Treating a selectively exposed resist with a developer conventionally involves depositing the liquid developer solution over the resist clad substrate and spinning the substrate whereby the liquid developer solution and dissolved areas of the resist are removed from the substrate by centrifugal forces. A rinsing solution, typically deionized water, is then deposited over the resist clad substrate and the substrate is spun again to remove the water and any debris solubilized by the water. Spinning the substrate is a convenient and inexpensive method of removing materials from substrate.
The patterned resist covered substrate is then subject to standard semiconductor processing such as material deposition, etching, or doping. Since the patterned resist only covers a portion of the substrate, the standard semiconductor processing techniques impact desired areas of the substrate. This is the basis for fabricating integrated circuit chips.
Prior to subjecting the patterned resist covered substrate to standard semiconductor processing, the patterned resist is inspected to ensure that certain requirements/parameters are satisfied. For example, the patterned resist may be inspected to access one or more of pattern position accuracy, feature size control, feature edge roughness, and defect density. One aspect of feature size control is critical dimension control, which is measured/accessed using a scanning electron microscope (SEM) or an atomic force microscope (AFM). SEMs and AFMs use an electron beam for generating images (both in projection and detection).
However, electrostatic charges build up on the patterned photoresist by the interaction of the electron beam with the photoresist material. Negative charges are particularly encountered on patterned photoresists. Electrostatic charge accumulation on patterned photoresists can be as high as 300-400 volts/cm
2
. This undesirable charge accumulation attracts airborne defects, even in a vacuum, onto the patterned photoresists. Such defects at best deleteriously effect the critical dimension control measurement of photoresist features, and at worst cause fatal defects during subsequent standard semiconductor processing.
Moreover, even in instances where there are no electrostatic charges associated with the patterned photoresist, airborne defects, such as carbon containing particles, may interfere with critical dimension control measurements. Airborne defects may be attributable to insufficient prior cleaning, or to a previously processed patterned photoresist.
SUMMARY OF THE INVENTION
The present invention provides systems and a cleaning process to improve critical dimension control measurements. The systems and processes of the present invention minimize and/or eliminate debris within an SEM or AFM chamber when a charge measurement indicates that the presence of such debris is likely. The present invention also provides systems and methods for detecting and minimizing the presence of defects on patterned resist covered semiconductor substrates. As a result of the present invention, inspection of patterned resists and post-lithography semiconductor processing are substantially improved.
One aspect of the present invention relates to a method of inspecting a patterned substrate using an SEM, involving the steps of evaluating the patterned substrate to determine if charges exist thereon; introducing the patterned substrate having charges thereon into a processing chamber of the SEM; inspecting the patterned resist using an electron beam generated by the SEM; and introducing a cleaner containing ozone into the processing chamber of the SEM.
Another aspect of the present invention relates to a method of improving critical dimension measurements of a patterned resist using an SEM, involving the steps of providing a semiconductor structure having a patterned resist thereon in a processing chamber of the SEM; evaluating the semiconductor structure having the patterned resist thereon to determine if electrostatic charges exist on the patterned resist; measuring the critical dimension of the patterned resist on the semiconductor structure using the SEM; and introducing a cleaner in a form of at least one of a gas and a plasma into the processing chamber while measuring the critical dimension, the cleaner containing ozone, and optionally at least one inert gas thereby reducing an amount of debris on the patterned resist.
Yet another aspect of the present invention relates to a system for processing a patterned substrate, containing a charge sensor for determining if charges exist on the patterned substrate and measuring the charges; a means for contacting the patterned substrate with a cleaner containing ozone to reduce the charges thereon; a controller for setting at least one of time of contact between the patterned substrate and the cleaner, temperature of the cleaner, concentration of ozone in the cleaner, and pressure under which contact between the patterned substrate and the cleaner occurs; and a device for inspecting the patterned substrate with an electron beam.
Still yet another aspect of the present invention relates to a system for processing a semiconductor substrate having a patterned resist thereon, containing a charge sensor for determining if electrostatic charges exist on the patterned resist and measuring the electrostatic charges; a means for contacting the patterned resist with a cleaner containing ozone to reduce the electrostatic charges thereon; a microprocessor-controller for setting at least one of time of contact between the patterned resist and the cleaner, temperature of the cleaner, concentration of ozone in the cleaner, and pressure under which contact between the patterned resist and the cleaner occurs; and a scanning electron microscope for inspecting the patterned resist with an electron beam.
REFERENCES:
patent: 4778536 (1988-10-01), Grebinski
patent: 4827371 (1989-05-01), Yost
patent: 5037506 (1991-08-01), Gupta et al.
patent: 5346586 (1994-09-01), Keller
patent: 5356478 (1994-10-01), Chen et al.
patent: 5423944 (1995-06-01), Wong
patent: 5486267 (1996-01-01), Knight et al.
patent: 5712198 (1998-01-01), Shive et al.
patent: 5753137 (1998-05-
Choo Bryan K.
Phan Khoi A.
Rangarajan Bharath
Singh Bhanwar
Subramanian Ramkumar
Advanced Micro Devices , Inc.
Amin, Eschweiler & Turocy, LLP
Rutledge D.
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