Radiation imagery chemistry: process – composition – or product th – Imaging affecting physical property of radiation sensitive... – Removal of imaged layers
Reexamination Certificate
2000-01-31
2002-07-23
Duda, Kathleen (Department: 1756)
Radiation imagery chemistry: process, composition, or product th
Imaging affecting physical property of radiation sensitive...
Removal of imaged layers
C430S322000, C134S001000
Reexamination Certificate
active
06423479
ABSTRACT:
TECHNICAL FIELD
The present invention generally relates to improved lithography processing. In particular, the present invention relates to reducing carbon contamination on lithography masks using sulfur trioxide.
BACKGROUND ART
Microlithography processes for making miniaturized electronic components, such as in the fabrication of computer chips and integrated circuits, are of increasing importance as the trend towards miniaturization and integration continues. Lithography involves the use of resists to temporarily mask a semiconductor substrate surface to enable site specific additive, subtractive, or enhancing processing (e.g., deposition, etching, doping). Lithography specifically involves applying a coating or film of a resist using a mask to a substrate material, such as a silicon wafer used for making integrated circuits. The substrate may contain any number of layers or devices thereon.
The resist coated substrate is baked to evaporate any solvent in the resist composition and to fix the resist coating onto the substrate. The baked coated surface of the substrate is next subjected to selective radiation through a mask; that is, an image-wise exposure to radiation using a lithography mask to create the image. This radiation exposure causes a chemical transformation in the exposed areas of the resist coated surface. Types of radiation commonly used in microlithographic processes include visible light, ultraviolet (UV) light and electron beam radiant energy. Masks are conventionally made of a pellicle encapsulated patterned chromium layer over a quartz substrate or a fused silicon substrate, wherein the patterned chromium layer is formed using a resist.
After selective exposure, the resist coated substrate is treated with a developer solution to dissolve and remove either the radiation-exposed or the unexposed areas of the resist (depending upon whether a positive resist or a negative resist is utilized) resulting in a patterned or developed resist. Many developer solutions contain water and a base, such as water and a hydroxide compound.
Treating a selectively exposed resist with a developer conventionally involves depositing the liquid developer solution over the resist clad substrate and spinning the substrate whereby the liquid developer solution and dissolved areas of the resist are removed from the substrate by centrifugal forces. A rinsing solution, typically deionized water, is then deposited over the resist clad substrate and the substrate is spun again to remove the water and any debris solubilized by the water. Spinning the substrate is a convenient and inexpensive method of removing materials from substrate.
The patterned resist covered substrate is then subject to standard semiconductor processing such as material deposition, etching, or doping. Since the patterned resist only covers a portion of the substrate, the standard semiconductor processing techniques impact desired areas of the substrate. This is the basis for fabricating integrated circuit chips.
After standard semiconductor processing (material deposition, etching, or doping) is completed, the patterned resist is removed or stripped from the substrate. This process is repeated numerous times until a desired product is obtained. Often times masks are used over and over again, until the number/size of defects on the mask becomes fatally large. Due to repeated exposure by light, a form of energy, charges are formed on masks. Various contaminating particles are attracted to these charges, causing defects on the mask.
It is desirable to use a mask as many times as possible. This is because masks are becoming increasingly difficult to fabricate, given the small features required and the current limitations of lithography. Maintaining continuous production is important and requires a mask free of contamination. Other important parameters associated with making and using masks include pattern position accuracy, feature size control, and defect density. In sum, fabricating a mask is complex and costly. And using more than one mask to make the same feature in different wafers raises repeatability concerns. Therefore it is desirable to use every lithography mask as much as possible.
Defects on masks, such as the accumulation of carbon containing contaminants, are caused by a number of factors including the laser employed to irradiate and underlying photoresist. As the trend to miniaturization continues, smaller and smaller contaminant particles constitute defects on lithography masks. Attempts are therefore made to maintain and clean masks. However, there are concerns associated with mask cleaning. For example, cleaning schemes are intended to effectively clean mask, prevent re-deposition of contaminant particles, prevent damage to the mask, and minimize safety and environmental hazards. Successfully achieving all of the goals is difficult.
While attempts at cleaning masks are made, it is noted that cleaning a lithography mask is different from cleaning a wafer. In this connection, cleaning a lithography mask requires attending to chromium and chromium oxide surfaces whereas cleaning wafers generally does not, cleaning a lithography mask requires zero defects whereas cleaning wafers generally does not, and the square/rectangular shaped surfaces of masks are difficult to clean using spray processes (lithography masks generally contain a much higher density of square/rectangular shaped surfaces than wafers). Accordingly, cleaning processes useful for wafers are not necessarily applicable to cleaning lithography masks.
SUMMARY OF THE INVENTION
The present invention provides an improved cleaning process in connection with lithography. The present invention also provides methods for minimizing the presence of carbon contaminants on lithography masks. As a result of the present invention, lithography masks are improved by substantially increasing the number of times any given lithography mask can be used. Therefore, also as a result of the present invention, improved repeatability with regard to making large batches of integrated circuit chips is achieved.
In one embodiment, the present invention relates to a method of processing a lithography mask, involving the steps of exposing a lithography substrate with actinic radiation through the lithography mask in a chamber; removing the lithography mask from the chamber, wherein the lithography mask contains carbon contaminants; and contacting the lithography mask with sulfur trioxide thereby reducing the carbon contaminants thereon.
In another embodiment, the present invention relates to a method of reducing carbon contaminants on a lithography mask, involving the steps of exposing a lithography substrate having a resist thereon with actinic radiation through the lithography mask in a chamber; removing the lithography mask from the chamber, wherein the lithography mask contains carbon contaminants; and contacting the lithography mask with a gas comprising from about 1% to about 100% by weight of sulfur trioxide and from about 0% to about 99% by weight of at least one inert gas thereby reducing the amount of carbon contaminants thereon.
In yet another embodiment, the present invention relates to a method of reducing carbon contaminants on a lithography mask, involving the steps of exposing a lithography substrate having a resist thereon with actinic radiation through the lithography mask in an exposure chamber; removing the lithography mask from the exposure chamber, wherein the lithography mask contains carbon contaminants; and contacting the lithography mask with a plasma comprising from about 10 sccm to about 10 slm of sulfur trioxide and from about 0 sccm to about 10 slm of at least one inert gas thereby reducing the amount of carbon contaminants thereon.
REFERENCES:
patent: 4778536 (1988-10-01), Grebinski
patent: 5037506 (1991-08-01), Gupta et al.
patent: 5356478 (1994-10-01), Chen et al.
patent: 5753137 (1998-05-01), Ye et al.
patent: 5763016 (1998-06-01), Levenson et al.
patent: 5849639 (1998-12-01), Molloy et al.
Choo Bryan K.
Phan Khoi A.
Rangarajan Bharath
Singh Bhanwar
Subramanian Ramkumar
Amin & Turocy LLP
Duda Kathleen
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