Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Reexamination Certificate
2003-10-17
2004-10-19
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
C365S225700, C365S149000
Reexamination Certificate
active
06807113
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a clamping circuit for the Vpop voltage used to program antifuses in an electronic circuit.
BACKGROUND OF THE INVENTION
There are many electronic circuits or integrated circuits (ICs) that utilize antifuses to set or program a piece of logic to a specific value. Antifuses are capacitive-type structures which, in their unblown state, form open circuits. Antifuses are programmed/blown by applying a high voltage across the antifuse. The high voltage causes the capacitive-type structure to break down, forming a conductive path through the antifuse. Therefore, programmed/blown antifuses conduct while unprogrammed/unblown antifuses do not. One circuit, for example, that uses antifuses is a memory circuit.
Typical memory circuits include arrays of memory cells arranged in rows and columns. These memory circuits will also include several redundant rows and columns that are used as substitutes for defective locations in the memory array. When a defective memory array location is identified, rather than treating the entire array as defective, a redundant row or column is substituted for the defective row or column. This substitution is performed by assigning the address of the defective row or column to the redundant row or column such that, when an address signal corresponding to the defective row or column is received, the redundant row or column is addressed instead.
To make the substitution of the redundant row or column substantially transparent to a system including the memory circuit, the memory circuit utilizes an address detection circuit. The address detection circuit monitors row and column addresses and enables redundant rows or columns if the address of a defective row or column is detected.
FIG. 1
illustrates the typical memory circuit
10
including an address detection circuit
20
, control and address circuitry
12
, an array of memory cells
14
and row and columns of redundant memory cells
16
.
One type of address detection circuit
20
is a fuse-bank address detection circuit. A fuse-bank address detection circuit utilizes several fuse-bank circuits to control the redundant rows and columns. Each fuse-bank circuit corresponds to one of the redundant rows or columns. If there are eight redundant rows and eight redundant columns, for example, then the address detection circuit
20
will include sixteen fuse-bank circuits. Each fuse-bank circuit includes a bank of sense lines, each sense line connected to a respective fuse. Each sense line corresponds to one bit of a memory address since each fuse-bank will be programmed with an address of a defective memory array location. If an address comprises eight bits, then each fuse-bank circuit includes eight sense lines, each with corresponding fuses.
The sense lines are “programmed” by blowing fuses in a pattern corresponding to the address word of the defective row or column (hereinafter referred to as the programmed addresses). The programmed addresses are then detected by initially applying a test voltage across the bank of sense lines. Then, bits of an external address are applied to the sense lines. If the pattern of blown fuses corresponds exactly to the pattern of external bits, a redundant match will be detected and the output signal will switch to a high state. Otherwise, if at least one external address bit does not correspond to its respective blown fuse, a non-match will be detected and the output signal will be in a low state. Therefore, a high voltage indicates that the programmed address matches the external address while a low voltage does not. A matched address indicates that the redundant row or column should be used.
To save the costs and labor required to blow the conventional fuse, antifuses have replaced fuses in the address detection circuit
20
.
FIG. 2
illustrates an antifuse circuit
30
used in an antifuse-bank circuit. The circuit
30
corresponds to one bit of a programmed address. As previously stated, if an address consisted of eight bits, then each antifuse-bank circuit would include eight antifuse circuits
30
. An antifuse
32
, illustrated in its unprogrammed (i.e., unblown) state, is connected to a switchable signal line often referred to as a common ground line (hereinafter “CGND line) and a latch circuit
34
. During normal operation, the CGND line is held at a ground potential to provide a reference for the antifuse
32
. To program the antifuse
32
, the CGND line is supplied with a high voltage sufficient enough to cause the capacitive-type structure of the antifuse
32
to break down. Generally, the high voltage used to program the antifuse is referred to as a programming voltage (Vpop).
Once programmed, the antifuse
32
has a known impedance, plus or minus a predetermined margin, which is detected by the latch circuit
34
. When strobed by logic in the address detection circuit
20
(FIG.
1
), the latch circuit
34
detects the impedance of the antifuse
32
and outputs an output signal that is either a logical “1” if the antifuse is programmed or a logical “0”, if the antifuse is not programmed. This output signal when combined with the output signals of the remaining antifuse circuits
30
of the antifuse-bank circuit forms an address of a defective memory location (i.e., a programmed address). The operation of antifuses in an address detection circuit
20
is described, for example, in U.S. Pat. No. 5,734,617 (Zheng), U.S. Pat. No. 5,742,555 (Marr et al.), and U.S. Pat No. 5,706,238 (Cutter et al.), all assigned to Micron Technology Inc. and incorporated by reference herein.
In some ICs, the CGND line is directly accessible before the device is packaged (e.g., still in wafer form). During initial testing and repair, the CGND line is connected to directly using a probe card. This is referred to herein as “direct-connect” programming or a first programming mode of operation. In direct-connect programming, the probe card provides the programming voltage Vpop to the CGND line, which is used to program the appropriate antifuse. After the device is packaged, however, the direct connection to the CGND line cannot be made. Because it is desirable to make repairs to the packaged product, manufacturers will include a backdoor mechanism for applying the programming voltage Vpop to the internal CGND line from an external device. This is referred to herein as “external” programming or a second programming mode and is provided via a pin on the external package.
The backdoor mechanism typically includes a booting circuit connected between the external connection (i.e., pin/pad) and the CGND line. During normal operation of the packaged IC, the booting circuit isolates the external pin/pad from the internal CGND line. During a test mode of the packaged part, when it is desirable to program antifuses (i.e., during the second programming mode), the booting circuit receives the programming voltage Vpop from the external pin/pad and passes the voltage Vpop to the CGND line. Typically, the booting circuit uses a pass gate transistor to connect the external pad to the CGND line. The pass gate transistor is “booted” (i.e., has its gate voltage capacitively driven to an elevated level to turn it on to a preferred strength (a certain voltage from its gate to its source) and avoid any threshold voltage loss across the device) by a booting capacitor circuit.
Unfortunately, due to the self-booting nature of portions of the booting circuit, when the unpackaged memory device is being programmed by the directly connected probe (e.g., during direct-connect programming or first programming mode), the voltage on the CGND line is passed onto the external pad. This very high voltage is seen across the electrostatic discharge (ESD) device of the pad, which can breakdown and limit the programming voltage Vpop. Limiting the programming voltage Vpop increases the time required to program the antifuses and decreases the resistance distribution in blown antifuses. Both of these side effects are undesirable.
Accordingly, there is a desire and need for a bootin
Cowles Timothy B.
Koelling Jeffrey
Dickstein , Shapiro, Morin & Oshinsky, LLP
Le Vu A.
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