Clamping circuit for stacked NMOS ESD protection

Details Clamping circuit for stacked NMOS ESD protection Clamping circuit for stacked NMOS ESD protection

2002-02-01

2004-06-08

Sircus, Brian (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

C361S056000

Reexamination Certificate

active

06747857

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates generally to a structure of and manufacturing process for a semiconductor device which provides improved ESD protection of active semiconductor devices and more particularly to a signal gate ground clamping element for cascaded metal oxide semiconductor (MOS) circuit configuration.
(2) Description of Prior Art
Because of high input impedance and thin oxide gate structures, the problem of Electrostatic Discharge (ESD) damage with field effect transistor (FET) devices can be severe. Therefore the input/output (I/O) circuit locations or pads usually have a protective device connected between the I/O pad and the internal circuits which allows the ESD current to be shunted to ground Another important characteristic of the ESD protection device is that it must not interfere with the operation of the devices it is designed to protect, while at the same time providing good protection when abnormal or ESD voltage incidents occur.
Typical ESD protection devices consist of a N channel metal oxide semiconductor (NMOS) connected to I/O pad A parasitic NPN bipolar device is essentially in parallel with the NMOS device which has a collector base breakdown triggered by the ESD voltage. Once triggered by an ESD incident, the parasitic device operates in a secondary breakdown mode to clamp the ESD voltage to a suitable level and pass the high current to a second voltage source, typically ground.
Integrated logic circuits frequently have a complimentary MOS output string as typified in
FIG. 1
utilizing “used” or active devices PMOS PU
1
, first or cascaded NMOS NU
1
, second or switched NMOS NU
2
, and “unused” or “dummy” I/O strings represented by devices PMOS PD
1
, first unused NMOS ND
1
, and second unused NMOS ND
2
. In addition to the complimentary PMOS PU
1
and NMOS NU
2
signal driven switching devices in the active I/O, the “used” logic string shown in
FIG. 1
also has a cascaded first NMOS NU
1
in series with the switched second active or “used” NMOS NU
2
. The gate of first NMOS NU
1
has its gate tied to Vcc. This cascaded FET NU
1
provides flexibility in circuit logic voltage levels while utilizing a specific FET device design.
In addition to the “used” or active I/O string, a “Dummy I/O” or inactive device string is shown in FIG.
1
. The string is comprised of a PMVOS PD
1
with its gate and drain tied too Vcc, and its source tied to the output pad
1
and to the drain of the cascaded firs “unused or dummy NMOS ND
1
. The source of the cascaded NMOS ND
1
is tied to the lower second “mused” NMOS ND
2
. The gate and source of NMOS ND
2
are tied to ground.
Referring to the “used” device string, a high logic level signal from the internal circuit, typically 3.3 V or 5V, will turn on the second NMOS NU
2
in the “used” or active string essentially pulling the output pad
1
voltage down to ground. The same logic signal assures that the PMOS PU
1
is turned off preventing any current flow in the string except during the switching transition. Conversely, a low logic signal from die internal circuit will turn on PMOS PU
1
and turn off the NMOS NU
2
presenting a voltage at or near Vcc at the output pad.
If an ESD event occurs while the second “used” NMOS NU
2
is turned on, high current can flow through the device with the potential for device damage. In addition, even with the device in the off state, a phenomenon known as hot carrier gate tunneling may turn the device on during an ESD event The hot carrier gate tunneling is caused by a high voltage such as produced by an ESD event, being placed on the drain of the NMOS NU
2
. Carriers gain sufficient energy to cause a positive charge or voltage to accumulate on the gate. This hot carrier gate tunneling positive gate voltage could turn the NMOS NU
2
device on, again exposing the device to damage from high ESD current This gate action is detrimental to ESD protection, and damage can possibly occur to one or more devices in the string. A device and method is described which greatly enhances the ESD protection capability of the cascaded NMOS device circuitry and limits the possibility of ESD damage to these devices.
The following patents describe ESD protection devices.
U.S. Pat. No. 6,008,974 (Lee et al.) describes a CMOS ESD output protection circuit with a clamping circuit to prevent NMOS damage. The clawing circuit comprises an NMOS transistor, a resistor, and a diode.
U.S. Pat. No. 5,986,867 (Duvvury) discloses an output protection circuit where an NMOS transistor is used as a dummy device.
U.S. Pat. No. 6,091,594 (Williamson et al) shows a CMOS ESD protection circuit where a cascaded NMOS stack is used.
U.S. Pat. No. 6,078,487 (Partovi et al.) shows an ESD circuit with an ESD clamp.
U.S. Pat. No. 6,091,595 (Sharpe Geisler) shows an ESD protection circuit for a 5V output buffer.
U.S. Pat. No. 5,610,790 (Staab et al.), U.S. Pat. No. 6,008,970 (Maloney et al.), and U.S. Pat. No. 5,708,550 (Avery) show related ESD circuits.
SUMMARY OF THE INVENTION
Accordingly, it is the primary objective of the invention to provide a novel effective circuit structure, and a circuit development method, for protecting integrated circuits from damage caused by ESD events occurring during circuit operation.
In addition, it is an objective of this invention to provide this ESD protection while maintaining appropriate normal circuit operating parameters of the devices being protected.
It is yet another object of the invention to provide a process method for forming the ESD protection structure that is fully compatible with the manufacturing process of the devices being protected.
The above objectives are achieved in accordance with the embodiments of the invention that describes a process and novel structure for a clamping FET device for the active signal switched NMOS transistor of the complimentary output inverter of CMOS logic devices. A NMOS clamping device has the drain connected to the gate of the output circuit string active switching NMOS that is normally controlled by the signal from the internal circuits. Therefore, the drain of the clamping NMOS device is also connected to the internal circuit signal line. The gate of the clamping device is connected to the output pad through a P−N diode with the diode negative N side connected to the I/O pad. The NMOS device gate is also connected to a second voltage source, typically ground, through a resistor. The source of the NMOS clamping device is connected directly to ground.
A high voltage from an ESD event causes the diode to operate in reverse breakdown mode thereby conveying a positive voltage to the gate of the clamping device turning it on enabling the active switched NMOS gate to be clamped to ground. Clamping the active NMOS gate to ground prevents the output device from being turned on during the duration of the ESD event by either a logic signal from the internal circuit or the hot carrier effect from the high ESD voltage on the drain. The resistor from the clamping device gate to ground provides the clamping device turn on voltage from the ESD event. The resistor is also in series with the diode, and therefore limits the current generated by the ESD event to protect the diode from damage.
During normal circuit operation the gate of the clamping device is shielded from normal logic signals by the diode, and is essentially grounded through the resistor assuring that the clamping device is in an off state. This prevents any interference with the normal I/O and logic circuit operational characteristics.


REFERENCES:
patent: 5173755 (1992-12-01), Co et al.
patent: 5444591 (1995-08-01), Chokhawala et al.
patent: 5610790 (1997-03-01), Staab et al.
patent: 5708550 (1998-01-01), Avery
patent: 5930094 (1999-07-01), Amerasekera et al.
patent: 5986867 (1999-11-01), Duvvury et al.
patent: 6008970 (1999-12-01), Maloney et al.
patent: 6008974 (1999-12-01), Lee et al.
patent: 6078487 (2000-06-01), Partovi et al.
patent: 6091594 (2000-07-01), Williamson et al.
patent: 6091595 (2000-07-01), Sharpe-Geisler
patent:

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