Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-04-03
2007-04-03
Lin, Sun James (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
10758977
ABSTRACT:
Digital circuits with time multiplexed redundancy and methods and apparatuses for their automated designs generated from single-channel circuit designs. At least one embodiment of the present invention includes a digital circuit which detects or corrects transitory upsets through time-multiplexed resource sharing. In one embodiment of the present invention, time-multiplexed resource sharing is used to reduce the die area for implementing modular redundancy. One embodiment of the present invention automatically and efficiently synthesizes multi-channel hardware for time-multiplexed resource sharing by automatically generating a time-multiplexed design of multi-channel circuits from the design of a single-channel circuit, in which at least a portion of the channels are allocated for modular redundancy.
REFERENCES:
patent: 5796935 (1998-08-01), Morrison et al.
patent: 6654910 (2003-11-01), Eibach et al.
Lyons et al., “The Use of Triple-Modular Redundancy to Improve Computer Reliability,” IBM Journal, Apr. 1962, pp. 200-209.
Habinc, “Functional Triple Modular Redundancy (FTMR)” Gaisler Research, Version 0.2, Dec. 2002, 56 pgs.
Franco, et al., “FPGA Implementation of a Serial Organized DA Multichannel FIR Filter,” Tenth ACM International Symposium on Field Programmable Gate Arrays, Monterey, California, Feb. 24-26, 2002.
Halperin, et al., “Combinatorial Approximation Algorithms for the Maximum Directed Cut Problem,” Proceedings of 12thSymposium on Discrete Algorithms, pp. 1-7, 2001.
Parhi, Keshab K., “VLSI digital signal processing systems: design and implementation,” Wiley-Interscience, pp. 91-118 & 149-187, 1999.
Thornton, James E., “Parallel Operation in the Control Data 6600,” AFIPS Proc. FJCC, pt. 2, vol. 26, pp. 33-40, 1964.
Weaver, Nicholas; Markovskiy, Yury; Patel, Yatish; Wawrzynek, John; “Post-Placement C-Slow Retiming for the Xilinx Virtex FPGA” 10 pages. Copyright 2003 ACM 1-58113-651—X/03/0002 FPGA '03, Feb. 23-25, Monterey, California USA.
Notification to Pay Additional Fees for International Application No. PCT/US2004/0100006, mailed Jun. 23, 2005, 8 pages. European Patent Office, Rijswijk. Authorized Officer: Iveta Bujanska.
Shalash, Ahmad F., et al., “Power Efficient Fir Folding Transformation For Wireline Digital Communications”, Copyright 1998 IEEE, 0-7803-5148-7/98, pp. 1816-1820.
Sundararajan, Vijay, et al.,“Synthesis of Low Power Folded Programmable Coefficient Fir Digital Filters”, Copyright 2000, IEEE, 0-7803-5973-9/00, pp. 153-156.
Lin, John, et al.,“A New Multi-Algorithm Multichannel Cascadable Digital Filter Processor”, IEEE 1988 Custom Integrated Circuits Conference, CH2584-1/88/0000-0060. Copyright 1988 IEEE. pp. 10.7.1-10.7.5.
Hassoun, Soha, et al., “Architectural Retiming: Pipelining Latency-Constrained Circuits” Copyright 1996 ACM, Inc. 0-89791-833-9/96/0006, pp. 708-713. 33rdDesign Automation Conference. XP-002330653.
Parhi, Keshab K., et al,“Synthesis of Control Circuits in Folded Pipeline DSP Architectures”, Copyright 1992 IEEE, 0018-9200/92503.00 vol. 27, No. 1, Jan. 1992. pp. 29-43.
PCT International Search Report and Written Opinion for PCT Appln No. US2004/010006, mailed Sep. 2, 2005 (18 pages).
Blakely , Sokoloff, Taylor & Zafman LLP
Lin Sun James
Synplicity, Inc.
LandOfFree
Circuits with modular redundancy and methods and apparatuses... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Circuits with modular redundancy and methods and apparatuses..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuits with modular redundancy and methods and apparatuses... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3746962