Circuits with dynamically biased active loads

Details Circuits with dynamically biased active loads Circuits with dynamically biased active loads

1996-02-14

1999-06-01

Santamauro, Jon

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

326 17, 326 83, 326121, 326113, 326 31, 326 32, 326 34, 326126, 326127, 327313, 327318, 327323, 327 65, 327 67, H03K 19094

Patent

active

059091274

ABSTRACT:
This invention provides a circuit and method to replace the passive resistive or statically biased active load devices with dynamically biased active load devices. This allows the load devices to present an effective load which varies depending on the state of the circuit output. The effective load and the time rate of change of the effective load can be dynamically optimized to improve circuit performance with changing conditions. The effective load is varied according to the state of the circuit by the use of time-delayed negative feedback. The biasing of the load devices is also capable to control the logic swing of the circuit. A bias generating circuit employing a dynamically biased active load is described. This provides a method for a family of logic circuits, especially CML circuits, to operate at low voltage and low power at high switching speeds, having symmetrical rise and fall times and well defined logic signal swings. The output is sampled and maintained at near ideal bias voltage with a voltage follower type circuit which provides a gain of less than unity and finite delay. Particular circuit implementations using various semiconductor technologies are described and many others are possible. Although the invention may find primary use in VLSI logic circuits, especially those requiring high speed and low power, it is also shown to be useful in analog circuits. Alternate circuit configurations for dynamically biased active load devices are described.

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