Circuits, systems, and methods for reducing simultaneous...

Details Circuits, systems, and methods for reducing simultaneous... Circuits, systems, and methods for reducing simultaneous...

2011-02-22

2011-02-22

Luu, Pho M (Department: 2824)

Static information storage and retrieval

Read/write circuit

Noise suppression

C365S226000, C365S227000, C365S228000, C365S229000

Reexamination Certificate

active

07894285

ABSTRACT:
Memory devices and methods are provided for reducing simultaneous switching output noise and power supply noise during burst data write and refresh operations. An embodiment of a memory device according to the present invention includes a first power domain coupled to some of the components of the memory device and a second power domain coupled to different components of the memory device. One or more distributed power domain coupling circuits may be coupled to the first and second power domains. The power domain coupling circuit includes a controller configured to generate an enable signal responsive to control signals, data signals, or any combination thereof. The power domain coupling circuit also includes coupling circuitry coupled to the first and second power domains and coupled to the controller. The coupling circuitry is configured to couple the first and second power domains together responsive to the enable signal.

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patent: 2004/0087420 (2004-10-01), None

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