Circuits, systems, and methods for reducing microprogram memory

Details Circuits, systems, and methods for reducing microprogram memory Circuits, systems, and methods for reducing microprogram memory

1997-01-09

1998-09-29

Lall, Parshotam S.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

39575003, 711 5, G06F 928, G11C 700

Patent

active

058156976

ABSTRACT:
A processor embodiment comprises a microprogram memory circuit (12) comprising a number of separately energizable banks (14a, 14b). Each of the number of separately energizable banks is operable to concurrently output at least one microinstruction. The processor further comprises circuitry for forming a microaddress for addressing the microprogram memory. This circuitry includes circuitry (26, 28) for identifying a value of a first bit (A0) and of a second bit (A1), and the microaddress comprises the first bit, the second bit, and a plurality of main bits (20c). Further, the processor includes circuitry for selectively energizing (24, 13a, 13b) a subset of the separately energizable banks in response to the value of the first bit, and the subset is less than the number of separately energizable banks. Still further, the processor includes circuitry (16) for outputting a first set of microinstructions from the subset of the separately energizable banks. Lastly, the processor includes circuitry (18) for selecting a subset of the first set of microinstructions in response to the value of the second bit, wherein the subset is less than the number of the first set of microinstructions.

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