Circuits, systems, and methods for re-mapping memory column redu

Details Circuits, systems, and methods for re-mapping memory column redu Circuits, systems, and methods for re-mapping memory column redu

1998-04-28

2000-04-25

Dinh, Son T.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36518902, 365200, 3652257, 36523002, G11C 800

Patent

active

060552042

ABSTRACT:
A memory configuration (304) comprising a row array (302) having a plurality of rows. The memory configuration further includes a plurality of memory columns (C.sub.0 through C.sub.4). Each of the plurality of rows is constructed to communicate a plurality of signals along the plurality of memory columns and each of the plurality of memory columns provides a memory column output. Further, the memory configuration includes a plurality of output columns (OC.sub.0 through OC.sub.3). Each of the plurality of output columns is operable to output a data signal external from the memory configuration. Still further, the memory configuration includes an encoder circuit (308) and a decoder circuit (306, M.sub.1 through M.sub.4). The encoder circuit identifies an identified one of the plurality of memory columns. The decoder circuit is responsive to the identified one of the plurality of memory columns identified by the encoder circuit, and couples selected ones of the plurality of memory columns to corresponding ones of the data columns. Particularly, the corresponding ones of the data columns include at least each of the plurality of memory columns other than the identified one of the plurality of memory columns.

REFERENCES:
patent: 4771404 (1988-09-01), Mano et al.
patent: 5050126 (1991-09-01), Tanaka et al.
patent: 5745401 (1998-04-01), Lee

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