Circuits, systems, and methods for external evaluation of microp

Details Circuits, systems, and methods for external evaluation of microp Circuits, systems, and methods for external evaluation of microp

1997-10-31

2000-05-09

Beausoliel, Jr., Robert W.

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

39550005, G06F 1100

Patent

active

060618116

ABSTRACT:
A microprocessor (10) operating in response to a clock signal (CLK) having a clock period. The microprocessor includes a readable memory (16), and this readable memory stores code (BIST) for performing diagnostic evaluations of the microprocessor. The diagnostic evaluations include a first evaluation to occur under non-failure operation at a first clock period (24) and a last evaluation to occur under non-failure operation at a last clock period (26). The microprocessor further includes circuitry (14) for issuing a series of addresses to the readable memory in order to address the code for performing diagnostic evaluations of the microprocessor. Still further, the microprocessor includes a conductor (D0) externally accessible and for providing a signal from the microprocessor. Lastly, the microprocessor includes circuitry (12) for outputting a diagnostic signal on the externally accessible conductor during performance of the diagnostic evaluations. Given the externally accessible conductor, divergence of the diagnostic signal from a predetermined pattern before the last dock period indicates a failure of the diagnostic evaluations before the last clock period.

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