Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1996-10-04
2003-01-28
Wright, Norman M. (Department: 2134)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S006130
Reexamination Certificate
active
06513130
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates in general to electronic memories and in particular to circuits, systems and methods for accounting for defective cells in a memory device.
BACKGROUND OF THE INVENTION
When integrating two or more blocks of circuitry into a single integrated circuit, one of the primary areas of concern is achieving a high integrated yield (i.e., the fabrication yield of the entire integrated circuit). Integrated yield becomes a particular concern when the blocks of circuitry being integrated are of different yielding designs and/or must be fabricated under different process rules. Since the integrated yield of a particular integrated circuit is a function of each of the non-integrated yields (i.e., the respective yields of each of the various types of circuitry blocks), it becomes important to maximize the yield of each type of circuitry being fabricated on the chip.
One specific case where integrated yield becomes a significant factor is when dynamic random access memory (DRAM) circuitry is being integrated with logic circuitry into a single chip. First, differences in yield between the logic circuitry and the DRAM circuitry result from differences in the actual designs of the circuits themselves. Second, differences in yields between the two type of circuits arise from the fact that logic circuitry and DRAM circuitry are typically fabricated using substantially different processes.
One way to increase the overall yield of integrated circuits including both logic circuitry and DRAM circuitry is to increase the yield of the DRAM circuitry by “repairing” defective memory cells in the DRAM cell array. Typically, a DRAM memory device has as many as 10% more “extra” rows of memory cells than specified. During production, a wafer test is performed to identify any rows which contain any defective cells. Any rows which are found to contain at least one defective cell are then “replaced” with an operative row taken from the extra rows in the array. This replacement may be performed for example by blowing fuses or otherwise physically altering the circuitry. This technique disadvantageously requires several production steps, including the time consuming steps of testing each cell array and replacing the bad rows with good rows by physically altering the chip. In sum, while such a technique can significantly increase the yield of a DRAM memory array, and hence the integrated yield of the chip, it also disadvantageously increases production time and device cost. At some point, depending on the number of defects, the time and expense required to repair a given memory array may become too time-consuming and/or too expensive and the device is simply discarded.
Thus, the need has arisen for circuits and methods which allow for increased yields of DRAM devices. In particular, such circuits and methods would increase integrated yields for integrated circuits including both logic and DRAM circuitry by increasing the yield of the DRAM memory array. Advantageously, such circuits and methods would help eliminate the time and expense currently required to physically alter the chip to replace bad rows of cells with good rows of cells.
SUMMARY OF THE INVENTION
According to the principles of the present invention, an associative memory system is used to “work around” bad rows and/or columns of cells in a memory cell array. For example, when an address is generated which calls for the access of a defective row of cells in a memory cell array, that address is translated to an address corresponding to a operative row of cells in the array. In a similar fashion, defective columns of cells in the memory array can be effectively “substituted” by directing any request to access such defective columns to operative columns in the same array. In the preferred embodiments, the associative memory is formed on the same integrated circuit as the memory array along with circuitry for testing the array for the existence of defective cells and programming circuitry to program the associative memory.
According to a first embodiment of the present invention, a data processing system is provided which includes an array of memory cells arranged in rows and columns, each row addressable by an address. Address generation circuitry is provided for generating addresses for accessing corresponding rows. An associative memory is coupled to the address generation circuitry for translating a first address, received from the address generation circuitry and addressing a defective one of the rows, into a second address addressing an operative one of the rows, the second address being sent to the memory.
According to a second embodiment of the present invention, a data processing system is provided which includes a controller for having address generation circuitry for generating addresses to access an associated memory. A memory system is provided which includes an array of memory cells arranged in rows and columns and decoding circuitry for selecting ones of the rows and columns in response to received ones of the addresses. The data processing system further includes associative memory circuitry operable to translate addresses received from the controller and addressing defective ones of the rows in a first space in the array into addresses addressing corresponding operative ones of the rows in a second space of the array.
According to a third embodiment of the present invention, a processing system is provided which includes a memory having an array of memory cells arranged in rows and columns, each column addressable by a column address. Address generation circuitry is also included for generating ones of the addresses for accessing corresponding selected ones of the columns. An associative memory is coupled to the address generation circuitry for translating a first address, received from the address generation circuitry and addressing a defective one of the columns, into a second address addressing an operative ones of the columns, the second address being presented to the memory.
The principles of the present invention are also embodied in methods for working around defective rows of cells in an array of memory cells arranged in rows and columns. First, an associative memory is programmed. A first row in the array of the memory is addressed and tested to determine that the first row contains at least one defective cell. A second address is generated for addressing a second row in the array. The first and second addresses are then stored in the associative memory such that the second address is output from the associative memory upon the input of the first address. The first address is then presented to the associative memory such that the second address is output therefrom to address the memory array. The second row of the memory array is then tested to ensure that the second row is operative. Next, an address is input to the associative memory to access at least one cell of a selected row of the array. If the address to the selected row matches an address to a defective row in the array, the address of a corresponding operative row is output to the memory array.
The principles of the present invention additionally provide a method of working around columns of defective cells in an array of memory cells arranged in rows and columns. First, an associative memory is programmed. Among other things, a first column in the memory array is addressed with a first address. That first address is tested to determine that the first column contains at least one defective cell. A second address is generated for addressing a second column in the array. The first and second addresses are then stored in the associative memory such that upon the input to the associative memory of the first address, the second address is output. The first address is then presented to the associative memory such that the second address is output to allow access to the second column in the array. The second column is then tested to ensure that the second column is operative. Upon the completion of the programming st
Cirrus Logic Inc.
Murphy, Esq. James J.
Winstead Sechrest & Minick P.C.
Wright Norman M.
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