Electrical computers and digital processing systems: memory – Address formation – Generating a particular pattern/sequence of addresses
Patent
1996-07-09
2000-05-02
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Address formation
Generating a particular pattern/sequence of addresses
711218, 711219, 711220, 395829, 345 1, G06F 1202
Patent
active
060584645
ABSTRACT:
An information processing system 400 includes a subsystem 402 having a processing resource 404 and a bus interface 403. An active logic mapping signal is presented to a mapping input bus interface 403. The system also includes a master processing device which is operable to write at least some bits of a starting address into bus interface 403, determine an ending address for subsystem 402 and lock subsystem 402.
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Chan Eddie P.
Cirrus Logic Inc.
Murphy James J.
Nguyen Than
Shaw Steven A.
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