Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2005-09-23
2010-11-23
Gurley, Lynne A (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S357000, C257S360000, C257SE29005, C257SE29018, C257SE21345, C257SE21618, C257SE27031, C257SE29062, C257SE29064
Reexamination Certificate
active
07838937
ABSTRACT:
Circuits including a laterally diffused output driver transistor and a distinct device configured to provide electrostatic discharge (ESD) protection for the laterally diffused output driver transistor are presented. In general, the device configured to provide ESD protection includes a drain extended metal oxide semiconductor transistor (DEMOS) transistor configured to breakdown at a lower voltage than a breakdown voltage of the laterally diffused output driver transistor. The laterally diffused output driver transistor may be a pull-down or a pull-up output driver transistor. The device also includes a silicon controlled rectifier (SCR) configured to inject charge within a semiconductor layer of the circuit upon breakdown of the DEMOS transistor. Moreover, the device includes a region configured to collect the charge injected from the SCR and further includes an ohmic contact region configured to at least partially affect the holding voltage of the SCR.
REFERENCES:
patent: 4990802 (1991-02-01), Smooha
patent: 5019888 (1991-05-01), Scott et al.
patent: 5043782 (1991-08-01), Avery
patent: 5140401 (1992-08-01), Ker et al.
patent: 5157573 (1992-10-01), Lee et al.
patent: 5173755 (1992-12-01), Co
patent: 5182220 (1993-01-01), Ker et al.
patent: 5218222 (1993-06-01), Roberts
patent: 5237395 (1993-08-01), Lee
patent: 5264723 (1993-11-01), Strauss
patent: 5289334 (1994-02-01), Ker et al.
patent: 5329143 (1994-07-01), Chan et al.
patent: 5444400 (1995-08-01), Hall
patent: 5576557 (1996-11-01), Ker et al.
patent: 5591992 (1997-01-01), Leach
patent: 5602404 (1997-02-01), Chen
patent: 5625522 (1997-04-01), Watt
patent: 5640299 (1997-06-01), Leach
patent: 5670799 (1997-09-01), Croft
patent: 5671111 (1997-09-01), Chen
patent: 5675469 (1997-10-01), Racino et al.
patent: 5682047 (1997-10-01), Consiglio et al.
patent: 5719733 (1998-02-01), Wei et al.
patent: 5754380 (1998-05-01), Ker et al.
patent: 5784242 (1998-07-01), Watt
patent: 5825600 (1998-10-01), Watt
patent: 6016002 (2000-01-01), Chen et al.
patent: 6066879 (2000-05-01), Lee et al.
patent: 6169309 (2001-01-01), Teggatz et al.
patent: 6281527 (2001-08-01), Chen
patent: 6365940 (2002-04-01), Duvvury et al.
patent: 6433368 (2002-08-01), Vashchenko et al.
patent: 6523266 (2003-02-01), Yang
patent: 6548874 (2003-04-01), Morton et al.
patent: 6576934 (2003-06-01), Cheng et al.
patent: 6642088 (2003-11-01), Yu
patent: 6696708 (2004-02-01), Hou et al.
patent: 6924531 (2005-08-01), Chen et al.
patent: 7375398 (2008-05-01), Wang et al.
patent: 7659558 (2010-02-01), Walker et al.
patent: 2002/0081783 (2002-06-01), Lee et al.
patent: 2004/0004231 (2004-01-01), Peng et al.
patent: 2004/0033666 (2004-02-01), Williams et al.
patent: 2005/0151160 (2005-07-01), Salcedo et al.
patent: 2005/0173765 (2005-08-01), Kim
patent: 2005/0174142 (2005-08-01), Jeon et al.
patent: 2005/0254189 (2005-11-01), Wu et al.
patent: 2005/0275029 (2005-12-01), Watt
patent: 2006/0006462 (2006-01-01), Chang et al.
patent: 2006/0274465 (2006-12-01), Wu et al.
patent: 2007/0069310 (2007-03-01), Song et al.
Duvvury et al., “Device Integration for ESD Robustness of High Voltage Power MOSFETs,” © 1994 IEEE, 4 pgs.
Lee et al., “Novel ESD Protection Structure with Embedded SCR LDMOS for Smart Power Technology,” 40th Annual International Reliability Physics Symposium, 2002, pp. 156-161.
USPTO Notice of Allowance for U.S. Appl. No. 11/233,959 dated Sep. 30, 2009; 7 pages.
USPTO Notice of Allowance for U.S. Appl. No. 11/233,959 dated Jun. 3, 2009; 7 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 11/233,959 dated Nov. 21, 2008; 7 pages.
USPTO Requirement for Restriction/Election for U.S. Appl. No. 11/233,959 dated Jun. 3, 2008; 6 pages.
USPTO Requirement for Restriction/Election for U.S. Appl. No. 11/233,959 dated Apr. 4, 2008; 6 pages.
USPTO Notice of Allowance for U.S. Appl. No. 08/845,302 dated May 19, 1998; 2 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 08/845,302 dated Feb. 6, 1998; 9 pages.
Duvvury et al., “ESD Phenomena and Protection Issues in CMOS Output Buffers,” 1987; pp. 174-180; 4 pages.
Duvvury et al., “Internal Chip ESD Phenomena Beyond the Protection Circuit,” 1988; pp. 2133-2138; 6 pages.
Polgreen et al., “Improving the ESD Failure Threshold of Silicided nMOS Output Transistors by Ensuring Uniform Current Flow,” 1989; pp. 167-174; 8 pages.
Duvvury et al., “Achieving Uniform nMOS Device Power Distribution for Sub-micron ESD Reliability,” 1992; 92-131 through 92-134; 4 pages.
Steven H. Voldman, “ESD Protection in a Mixed Voltage Interface and Multi-Rail Disconnected Power Grid Environment in 0.50- and 0.25-um Channel Length CMOS Technologies,” 1995; 94-125 through 94-134; 10 pages.
Dabral et al., “Core Claps for Low Voltage Technologies,” 1994; 94-141 through 94-149; 9 pages.
Voldman et al., “Mixed-Voltage Interface ESD Protection Circuits for Advance Microprocessors in Shallow Trench and LOCOS Isolation CMOS Technologies,” 1994; 94-277 through 94-280; 4 pages.
Jaffe et al., “Electrostatic Discharge Protection in a 4-MBIT Dram,” 1990; pp. 1-6; 6 pages.
LeBlanc et al., “Proximity Effects of ‘Unused’ Output Buffers on ESD Performance,” 1991; pp. 327-330; 4 pages.
Worley et al., “Sub-Micron Chip ESD Protection Schemes which Avoid Avalanching Junction,” 1995; 95-13 through 95-20; 8 pages.
Chatterjee et al., “A Low-Voltage Triggering SCR for On-Chip ESD Protection at Output and Input Pads,” 1991; pp. 21-22; 2 pages.
USPTO Notice of Allowance for U.S. Appl. No. 08/297,629 dated Oct. 28, 1996; 8 pages.
USPTO Final Rejection for U.S. Appl. No. 08/297,629 dated Jun. 10, 1996; 6 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 08/297,629 dated Sep. 12, 1995; 8 pages.
USPTO Notice of Allowance for U.S. Appl. No. 08/758,336 dated Dec. 4, 1997; 2 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 08/758,336 dated Aug. 13, 1997; 6 pages.
Tandan, “ESD Trigger Circuit,” EOS/ESD Symposium 1994, pp. 94-120 through 94-124; 5 pages.
Merrill et al., “ESD Design Methodology,” EOS/ESD Symposium 1993, pp. 93-233 through 93-237; 5 pages.
van Roozendaal et al., “Standard ESD Testing of Integrated Circuits,” 1990 EOS/ESD Symposium Proceedings, pp. 119-130; 12 pages.
Watt et al., “A Hot-Carrier Trigger SCR for Smart Power Bus ESD Protection,” Cypress Semiconductor Corporation, 1995 IEEE Electron Device Letters, vol. 12, No. 1, Jan. 1991; 4 pages.
Kutz Harold M.
Puchner Helmut
Shutt James H.
Walker Andrew J.
Cypress Semiconductor Corporation
Gurley Lynne A
Li Meiya
LandOfFree
Circuits providing ESD protection to high voltage laterally... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Circuits providing ESD protection to high voltage laterally..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuits providing ESD protection to high voltage laterally... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4230564