Circuits for improving read and write margins in multi-port...

Details Circuits for improving read and write margins in multi-port... Circuits for improving read and write margins in multi-port...

2006-11-13

2008-12-23

Yoha, Connie C (Department: 2827)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S202000

Reexamination Certificate

active

07468903

ABSTRACT:
A system and method for writing a SRAM cell coupled to complimentary first and second bit-lines (BLs) is disclosed, the method comprising asserting a word-line (WL) selecting the SRAM cell to a first positive voltage, providing a second positive voltage at the first BL, providing a first negative voltage at the second BL, and asserting a plurality of WLs not selecting the SRAM cell to a second negative voltage, wherein the writing margin of the SRAM cell is increased.

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Yamauchi, Hiroyuki et al., “0.5 V Single Power Supply Operated High-Speed Boosted and Offset-Grounded Data Storage (BOGS) SRAM Cell Architecture”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 5, No. 4, Dec. 1997, pp. 377-387.
Zhang, K., et al., “A 3-GHz 70Mb SRAM in 65nm CMOS Technology with Integrated Column-Based Dynamic Power Supply”, ISSCC 2005/Session 26/Non-Volatile Memory/26.1, Digest of Technical Papers, 2005 IEEE International Solid-State Circuits Conference, pp. 474-475, 611.

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