Circuits, architectures, apparatuses, systems, methods,...

Details Circuits, architectures, apparatuses, systems, methods,... Circuits, architectures, apparatuses, systems, methods,...

2007-04-25

2010-11-16

Tabone, Jr., John J (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S718000, C714S758000, C714S766000, C365S200000, C365S201000

Reexamination Certificate

active

07836364

ABSTRACT:
Circuits, architectures, systems, methods, algorithms, software and firmware for indicating positions of defective data storage cells using reserved (e.g., “pilot”) cells. The circuit generally includes a memory having multiple subunits, each subunit containing multiple data storage cells and at least one reserved cell. The reserved cells store information identifying whether one or more data storage cells in a subunit are defective. The method of identifying defective memory positions generally includes determining the status of data storage cells in a multi-subunit memory; storing such status information in a reserved cell; and reading the reserved cell. In various embodiments, the reserved cells differentiate between fewer voltage levels and/or store a lower density of information than the data storage cells. The present invention improves error correction capabilities using cells that are typically already available in many conventional nonvolatile memories. In some cases, marking data from defective cells as erasures effectively doubles the error correction capability of the system. When the reserved cells contain more than one level, the overhead for a given level of fault coverage decreases as a function of memory size.

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