Circuits, architectures, a system and methods for improved...

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction

Reexamination Certificate

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Reexamination Certificate

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07864912

ABSTRACT:
Circuits, architectures, a system and methods for clock data recovery. The circuit generally includes a clock phase adjustment circuit, receiving clock phase information and providing a clock phase adjustment signal, a clock frequency adjustment circuit, receiving clock frequency information and providing a clock frequency adjustment signal, and an adder circuit, receiving the clock phase adjustment signal and the clock frequency adjustment signal, and providing a clock recovery adjustment signal. The architectures and/or systems generally comprise those that include a clock data recovery circuit embodying one or more of the inventive concepts disclosed herein. The method generally comprises the steps of sampling the data stream at predetermined times, generating clock frequency information and clock phase information from sampled data, and altering a frequency and/or a phase of the clock signal in response to the clock frequency information and the clock phase information. The present invention prevents or reduces the likelihood of a potential nonconvergence/clock runaway problem, advantageously with minimal or no changes to existing designs and logic. The present invention further advantageously improves system stability, reliability and performance with a minimum of additional circuitry.

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Serial ATA Host Controller Solutions 88SX5080 information sheet, from www.marvell.com, Marvell Int'l.
Serial ATA Bridge Chip Solutions 88i8030 information sheet, from www.marvell.com, Marvell Int'l.

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