Circuits and systems for limited switch dynamic logic

Details Circuits and systems for limited switch dynamic logic Circuits and systems for limited switch dynamic logic

2002-04-04

2003-11-18

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S121000

Reexamination Certificate

active

06650145

ABSTRACT:

TECHNICAL FIELD
The present invention relates to dynamic logic circuits, and in particular, to dynamic logic circuits having a dynamic switching factor to reduce power consumption.
BACKGROUND INFORMATION
Modern data processing systems may perform Boolean operations on a set of signals using dynamic logic circuits. Dynamic logic circuits are clocked. During the pre-charge phase of the clock, the circuit is preconditioned, typically, by pre-charging an internal node of the circuit by coupling to a supply rail. During an evaluate phase of the clock, the Boolean finction being implemented by the logic circuit is evaluated in response to the set of input signal values appearing on the inputs during the evaluate phase. (For the purposes herein, it suffices to assume that the input signals have settled to their “steady-state” values for the current clock cycle, recognizing that the input value may change from clock cycle to clock cycle.) Such dynamic logic may have advantages in both speed and the area consumed on the chip over static logic. However, the switching of the output node with the toggling of the phase of the clock each cycle may consume power even when the logical value of the output is otherwise unchanged.
This may be a appreciated by referring to
FIG. 1.1
illustrating an exemplary three-input OR dynamic logic gate, and the accompanying timing diagram,
FIG. 1.2
. Dynamic logic
100
,
FIG. 1.1
, includes three inputs a, b and c coupled to a corresponding gate of NFETs
102
a
-
102
c
. During an evaluate phase of clock
104
, &phgr;
1
foot NFET
106
is active, and if any of inputs a, b or C is active, dynamic node
108
is pulled low, and the output goes “high” via inverter
110
. Thus, referring to
FIG. 1.2
, which is illustrative, at t
1
input a goes high during a pre-charge phase &phgr;
2
of clock
104
. (During the pre-charge phase &phgr;
2
of clock
104
, dynamic node
108
is pre-charged via PFET
112
. (Half-latch PFET
114
maintains the charge on dynamic node
108
through the evaluate phase, unless one or more of inputs a, b or c is asserted.) In the illustrative timing diagrams in
FIG. 1.2
, input a is “high” having a time interval t
1
through t
2
that spans approximately 2½ cycles of clock
104
, which includes evaluation phases,
116
and
118
. Consequently, dynamic node
108
undergoes two discharge-precharge cycles,
120
and
122
. The output node similarly undergoes two discharge-precharge cycles, albeit with opposite phase,
124
and
126
. Because the output is discharged during the pre-charge phase of dynamic node
108
, even though the Boolean value of the logical function is “true” (that is, “high” in the embodiment of OR gate
100
) the dynamic logic dissipates power even when the input signal states are unchanged.
Additionally, dynamic logic may be implemented in a dual rail embodiment in which all of the logic is duplicated, one gate for each sense of the data. That is, each logic element includes a gate to produce the output signal, and an additional gate to produce its complement. Such implementations may exacerbate the power dissipation in dynamic logic elements, as well as obviate the area advantages of dynamic logic embodiments.
Thus, there is a need in the art for circuits and systems which mitigate the dynamic switching factor of dynamic logic gates. Additionally, there is a further need for such circuits and systems that maintain the area advantage of dynamic logic over static circuits, and further provide both logic senses, that is, the output value and its complement.


REFERENCES:
patent: 5886540 (1999-03-01), Perez
patent: 5983013 (1999-11-01), Rogers et al.
Sigal et al., Circuit design techniques for the high-performance CMOS IBM S/390 Parallel Enterprise Server G4 microprocessor, IBM J. Res. Develop, vol. 41 No. 4/5, Jul./Sep. 1997, pp. 489-501.*
Durham-IBM, Figure—The 630FP Approach to Clocking and Latching, Domino Mid-Cycle Latch (DMCL),ARL Clocking&Latch Workshop, 03/18-20/97, p. 16.
Sigal et al., “Circuit design techniques for the high-performance CMOS IBM S/390 Parallel Enterprise Server G4 microprocessor,”IBM J. Res. Develop, vol. 41, No. 4/5, Jul./Sep. 1997, pp. 489-501.

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