Circuits and methods to protect a gate dielectric antifuse

Details Circuits and methods to protect a gate dielectric antifuse Circuits and methods to protect a gate dielectric antifuse

2006-10-24

2006-10-24

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Having fuse element

C365S145000, C365S189110

Reexamination Certificate

active

07126871

ABSTRACT:
According to embodiments of the present invention, an antifuse circuit is operated by coupling an elevated voltage to a first terminal of an antifuse, controlling current in the antifuse with a program driver circuit coupled to a second terminal of the antifuse, and shunting current around the antifuse with a bypass circuit coupled between the first terminal of the antifuse and the program driver circuit to protect the antifuse. The antifuse includes a layer of gate dielectric between the first terminal and the second terminal. The embodiments of the present invention protect a gate dielectric antifuse.

REFERENCES:
patent: 4748490 (1988-05-01), Hollingsworth
patent: 5110754 (1992-05-01), Lowrey et al.
patent: 5194759 (1993-03-01), El-Ayat et al.
patent: 5282158 (1994-01-01), Lee
patent: 5299150 (1994-03-01), Galbraith et al.
patent: 5376566 (1994-12-01), Gonzales
patent: 5379250 (1995-01-01), Harshfield
patent: 5439835 (1995-08-01), Gonzales
patent: 5646879 (1997-07-01), Harshfield
patent: 5661045 (1997-08-01), Manning et al.
patent: 5714786 (1998-02-01), Gonzales et al.
patent: 5724282 (1998-03-01), Loughmiller et al.
patent: 5741720 (1998-04-01), Hawley et al.
patent: 5742555 (1998-04-01), Marr et al.
patent: 5748025 (1998-05-01), Ng et al.
patent: 5789796 (1998-08-01), Kang et al.
patent: 5811869 (1998-09-01), Seyyedy et al.
patent: 5818778 (1998-10-01), Lui et al.
patent: 5838620 (1998-11-01), Zagar et al.
patent: 5859543 (1999-01-01), Kolze
patent: 5978248 (1999-11-01), Marr et al.
patent: 5990021 (1999-11-01), Prall et al.
patent: 5998274 (1999-12-01), Akram et al.
patent: 6005273 (1999-12-01), Gonzales et al.
patent: 6011289 (2000-01-01), Huang et al.
patent: 6011742 (2000-01-01), Zheng
patent: 6041008 (2000-03-01), Marr
patent: 6088282 (2000-07-01), Loughmiller et al.
patent: 6090693 (2000-07-01), Gonzales et al.
patent: 6194756 (2001-02-01), Gonzales
patent: 6233194 (2001-05-01), Marr et al.
patent: 6252293 (2001-06-01), Seyyedy et al.
patent: 6252422 (2001-06-01), Patel et al.
patent: 6255837 (2001-07-01), Habersetzer et al.
patent: 6271071 (2001-08-01), Gonzales
patent: 6285062 (2001-09-01), Marr
patent: 6300188 (2001-10-01), Gonzales
patent: 6384666 (2002-05-01), Bertin et al.
patent: 6448603 (2002-09-01), Gonzales
patent: 6456149 (2002-09-01), Cutter et al.
patent: 6515344 (2003-02-01), Wollesen
patent: 6515931 (2003-02-01), Marr et al.
patent: 6545928 (2003-04-01), Bell
patent: 6570805 (2003-05-01), McCollum
patent: 6630724 (2003-10-01), Marr
patent: 6751150 (2004-06-01), Marr et al.
patent: 2001/0051407 (2001-12-01), Tran
patent: 2001/0054740 (2001-12-01), Marr
patent: 2002/0027822 (2002-03-01), Candelier et al.
patent: 2003/0214841 (2003-11-01), Scheuerlein et al.
patent: 2004/0042317 (2004-03-01), Marr et al.
patent: 2005/0029598 (2005-02-01), Marr et al.
Candelier, P., et al., “One Time Programmable Drift Antifuse Cell Reliability”,IEEE International Reliability Physics Symposium Proceedings, San Jose, Ca,(2000),pp. 169-173.
Dabral, S. , et al.,Basic ESD and I/O design, John Wiley & Sons, Inc, New York,(1998),pp. 260-263.
Dabral, Sanjay , et al.,Basic ESD and I/O Design, (1998),pp. 272.
De Graaf, C. , et al., “A Novel High-Density Low-Cost Diode Programmable Read Only Memory”,IEDM Technical Digest, San Francisco, Ca,(1996),pp. 189-192.
Dobberpuhl, D. W., et al., “A 200-MHz 64-b Dual-Issue CMOS Microprocessor”,IEEE Journal of Solid-State Circuits, 27(11), (1992),pp. 1555-1567.
Hamdy , E. , et al., “Dielectric based antifuse for logic and memory ICs”,IEDM, San Francisco, Ca,(1988),pp. 786-789.
Hower, P. L., et al., “Snapback and Safe Operating Area of Ldmos Transistors”,IEDM, (1999),pp. 193-196.
Kalnitsky, A. , et al., “CoSi2 integrated fuses on poly silicon for low viltage 0.18 micrometer CMOS applications”,IEDM, (1999),pp. 765-768.
Lee, H. , et al., “THPM 13.4: An Experimental 1 Mb CMOS SRAM with Configurable Organization and Operation”,IEEE International Solid-State Circuits Conference, (1988),pp. 180-181, 359.
Ludikhuize, A. W., et al., “Analysis of hot-carrier-induced degradation and snapback in submicron 50V lateral MOS transistors”,IEEE, (1997),pp. 53-56.
Schroder, H U., et al., “High Voltage resistant ESD protection circuitry of 0.5um CMOS OTP/EPROM programming pin”,EOS/ESD Symposium, (1998),pp. 2A.6.1-2A.6.8.
Voldman, S. H., “ESD Protection in a Mixed Voltage Interface and Multi-Rail Diconnected Power Grid Environment in 0.50- and 0.25- micrometer Channel Length CMOS Technologies”,EOS/ESD Symposium, (1994),pp. 125-134.

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