Circuits and methods for selectively latching the output of...

Details Circuits and methods for selectively latching the output of... Circuits and methods for selectively latching the output of...

2002-07-31

2004-05-04

Tan, V. (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

C326S105000, C326S095000, C326S098000, C708S505000, C708S683000

Reexamination Certificate

active

06731138

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to adders, and more particularly, to circuits and methods for selectively latching the output of an adder.
BACKGROUND OF THE INVENTION
A microprocessor typically includes an arithmetic unit. The arithmetic unit typically includes an adder. A portion
10
of such an adder is shown in FIG.
1
.
The illustrated portion
10
of the adder includes first and second exclusive or (XOR) gates
12
,
14
. One of the XOR gates
12
,
14
develops an answer with a carry
1
signal. The other of the XOR gates
12
,
14
develops an answer with no carry
1
signal.
The output signals of the XOR gates
12
,
14
are respectively inverted by a pair of inverters
16
,
18
. The outputs of the inverters are coupled to a conventional sum select multiplexer
20
.
The multiplexer
20
is responsive to a select signal to output one of the input signals received from the first inverter
16
and the input signal received from the second inverter
18
. The output of the multiplexer
20
is inverted by an inverter
22
. The output of the inverter
22
is latched by a latch
24
.


REFERENCES:
patent: 5726586 (1998-03-01), Chan et al.
patent: 5751162 (1998-05-01), Mehendale et al.
patent: 6397241 (2002-05-01), Glaser et al.

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